米6体育平台手机版

ZHCSHV1A March 2018 – May 2018 SN65LVDS93B-Q1

PRODUCTION DATA.

封装选项

机械数据 (封装 | 引脚)

DGG|56
- MPDS570

散热焊盘机械数据 (封装 | 引脚)

订购信息

5 Pin Configuration and Functions

DGG Package

56-PIN (TSSOP)

(Top View)

Pin Functions

PIN		I/O	DESCRIPTION
NAME	NO.	I/O	DESCRIPTION
CLKIN	31	CMOS IN with pulldn	Input pixel clock; rising or falling clock polarity is selectable by Control input CLKSEL.
CLKOUTP	39	LVDS Out	Differential LVDS pixel clock output. Output is high-impedance when SHTDN is pulled low (de-asserted).
CLKOUTM	40	LVDS Out
CLKSEL	17	CMOS IN with pulldn	Selects between rising edge input clock trigger (CLKSEL = V_IH) and falling edge input clock trigger (CLKSEL = V_IL).
D5, D6, D7, D8 D9, D10, D11, D12 D13, D14, D15, D16 D17, D18, D19, D20 D21, D22, D23, D24 D25, D26, D27 D0, D1, D2, D3, D4	2, 3, 4, 6 7, 8, 10, 11 12, 14, 15 , 16 18, 19, 20, 22 23, 24, 25, 27 28, 30, 50 51, 52, 54, 55, 56	CMOS IN with pulldn	Data inputs; supports 1.8 V to 3.3 V input voltage selectable by VDD supply. To connect a graphic source successfully to a display, the bit assignment of D[27:0] is critical (and not necessarily intuitive). For input bit assignment see to for details. Note: if application only requires 18-bit color, connect unused inputs D5, D10, D11, D16, D17, D23, and D27 to GND.
GND	5, 13, 21, 29, 33, 35, 36, 43, 49, 53	Power Supply⁽¹⁾	Supply ground for VCC, IOVCC, LVDSVCC, and PLLVCC.
IOVCC	1, 26	Power Supply⁽¹⁾	I/O supply reference voltage (1.8 V up to 3.3 V matching the GPU data output signal swing)
LVDSVCC	44	Power Supply⁽¹⁾	3.3 V LVDS output analog supply
PLLVCC	34	Power Supply⁽¹⁾	3.3 V PLL analog supply
SHTDN	32	CMOS IN with pulldn	Device shut down; pull low (de-assert) to shut down the device (low power, resets all registers) and high (assert) for normal operation.
VCC	9	Power Supply⁽¹⁾	3.3 V digital supply voltage
Y0P	47	LVDS Out	Differential LVDS data outputs. Outputs are high-impedance when SHTDN is pulled low (de-asserted)
Y0M	48
Y1P	45
Y1M	45
Y2P	41
Y2M	42
Y3P	37	LVDS Out	Differential LVDS Data outputs. Output is high-impedance when SHTDN is pulled low (de-asserted). Note: if the application only requires 18-bit color, this output can be left open.
Y3M	38	LVDS Out

(1) For a multilayer pcb, it is recommended to keep one common GND layer underneath the device and connect all ground terminals directly to this plane.