ZHCSHV2A March 2018 – May 2018 SN65LVDS93B
PRODUCTION DATA.
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| VT | Input voltage threshold | RL = 100 Ω, See Figure 5 | IOVCC/2 | V | ||
| |VOD| | Differential steady-state output voltage magnitude | 250 | 450 | mV | ||
| Δ|VOD| | Change in the steady-state differential output voltage magnitude between opposite binary states | 1 | 35 | mV | ||
| VOC(SS) | Steady-state common-mode output voltage | See Figure 5
tR/F (Dx, CLKin) = 1 ns |
1.125 | 1.375 | V | |
| VOC(PP) | Peak-to-peak common-mode output voltage | 35 | mV | |||
| IIH | High-level input current | VIH = IOVCC | 25 | μA | ||
| IIL | Low-level input current | VIL = 0 V | ±10 | μA | ||
| IOS | Short-circuit output current | VOY = 0 V | ±24 | mA | ||
| VOD = 0 V | ±12 | mA | ||||
| IOZ | High-impedance state output current | VO = 0 V to VCC | ±20 | μA | ||
| Rpdn | Input pulldown integrated resistor on all inputs (Dx, CLKSEL, SHTDN, CLKIN) | IOVCC = 1.8 V | 200 | kΩ | ||
| IOVCC = 3.3 V | 100 | |||||
| IQ | Quiescent current | Disabled, all inputs at GND;
SHTDN = VIL |
10 | 100 | μA | |
| ICC | Supply current (average) | SHTDN = VIH, RL = 100 Ω (5 places), grayscale pattern (Figure 6)
VCC = 3.3 V, fCLK = 75 MHz |
||||
| I(VCC) + I(PLLVCC) + I(LVDSVCC) | 51.9 | mA | ||||
| I(IOVCC) with IOVCC = 3.3 V | 0.4 | |||||
| I(IOVCC) with IOVCC = 1.8 V | 0.1 | |||||
| SHTDN = VIH, RL = 100 Ω (5 places), worst-case pattern (Figure 7),
VCC = 3.6 V, fCLK = 75 MHz |
||||||
| I(VCC) + I(PLLVCC) + I(LVDSVCC) | 63.7 | mA | ||||
| I(IOVCC) with IOVCC = 3.3 V | 1.3 | |||||
| I(IOVCC) with IOVCC = 1.8 V | 0.5 | |||||
| SHTDN = VIH, RL = 100 Ω (5 places), worst-case pattern (Figure 7),
fCLK = 85 MHz |
||||||
| I(VCC) + I(PLLVCC) + I(LVDSVCC) | 75.1 | mA | ||||
| I(IOVCC) with IOVCC = 3.6 V | 1.5 | |||||
| I(IOVCC) with IOVCC = 1.8 V | 0.6 | |||||
| CI | Input capacitance | 2 | pF | |||