ZHCSHV2A March 2018 – May 2018 SN65LVDS93B
PRODUCTION DATA.
The data inputs to the transmitter come from the graphics processor and consist of up to 24 bits of video information, a horizontal synchronization bit, a vertical synchronization bit, an enable bit, and a spare bit. The data can be loaded into the registers upon either the rising or falling edge of the input clock selectable by the CLKSEL pin. Data inputs are 1.8 V to 3.3 V tolerant for the SN65LVDS93B and can connect directly to low-power, low-voltage application and graphic processors. The bit mapping is listed in Table 1.
RED | GREEN | BLUE | |
---|---|---|---|
LSB | R0 | G0 | B0 |
R1 | G1 | B1 | |
R2 | G2 | B2 | |
4-bit MSB | R3 | G3 | B3 |
R4 | G4 | B4 | |
6-bit MSB | R5 | G5 | B5 |
R6 | G6 | B6 | |
8-bit MSB | R7 | G7 | B7 |