ZHCSHV2A March 2018 – May 2018 SN65LVDS93B
PRODUCTION DATA.
| PIN | I/O | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| CLKSEL | 17 | I | Selects between rising edge input clock trigger (CLKSEL = VIH) and falling edge input clock trigger
(CLKSEL = VIL). |
| CLKIN | 31 | I | Input pixel clock; rising or falling clock polarity is selectable by Control input CLKSEL. |
| CLKOUTM | 40 | O | Differential LVDS pixel clock output.
Output is high-impedance when SHTDN is pulled low (de-asserted). |
| CLKOUTP | 39 | O | |
| D0 | 51 | I | Data inputs; supports 1.8-V to 3.3-V input voltage selectable by VDD supply. To connect a graphic source successfully to a display, the bit assignment of D[27:0] is critical (and not necessarily intuitive).
Note: if application only requires 18-bit color, connect unused inputs D5, D10, D11, D16, D17, D23, and D27 to GND |
| D1 | 52 | ||
| D2 | 54 | ||
| D3 | 55 | ||
| D4 | 56 | ||
| D5 | 2 | ||
| D6 | 3 | ||
| D7 | 4 | ||
| D8 | 6 | ||
| D9 | 7 | ||
| D10 | 8 | ||
| D11 | 10 | ||
| D12 | 11 | ||
| D13 | 12 | ||
| D14 | 14 | ||
| D15 | 15 | ||
| D16 | 16 | ||
| D17 | 18 | ||
| D18 | 19 | ||
| D19 | 20 | ||
| D20 | 22 | ||
| D21 | 23 | ||
| D22 | 24 | ||
| D23 | 25 | ||
| D24 | 27 | ||
| D25 | 28 | ||
| D26 | 30 | ||
| D27 | 50 | ||
| GND | 5, 13, 21, 29, 33, 35, 36, 43, 49, 53 | Power Supply(1) | Supply Ground for VCC, IOVCC, LVDSVCC, and PLLVCC. |
| IOVCC | 1, 26 | I/O supply reference voltage (1.8 V up to 3.3 V matching the GPU data output signal swing) | |
| LVDSVCC | 44 | 3.3-V LVDS output analog supply | |
| PLLVCC | 34 | 3.3-V PLL analog supply | |
| SHTDN | 32 | I | Device shut down; pull low (de-assert) to shut down the device (low power, resets all registers) and high (assert) for normal operation. |
| VCC | 9 | Power Supply(1) | 3.3-V digital supply voltage |
| Y0M | 48 | O | Differential LVDS data outputs.
Outputs are high-impedance when SHTDN is pulled low (de-asserted) |
| Y1M | 46 | ||
| Y2M | 42 | ||
| Y0P | 47 | ||
| Y1P | 45 | ||
| Y2P | 41 | ||
| Y3M | 38 | O | Differential LVDS Data outputs.
Output is high-impedance when SHTDN is pulled low (de-asserted). Note: if the application only requires 18-bit color, this output can be left open. |
| Y3P | 37 | ||