8.1 Overview

This is a single 2-input positive-NAND gate that is designed in Texas Instrument’s ultra-low power technology. It performs the Boolean function Y = A × B or Y = A + B in positive logic.

The AUP family of devices has quiescent power consumption less than 1 µA and comes in the ultra small DPW package. The DPW package technology is a major breakthrough in IC packaging. Its tiny 0.64 mm square footprint saves significant board space over other package options while still retaining the traditional manufacturing friendly lead pitch of 0.5 mm.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered. The I_off feature also allows for live insertion.

8.2 Functional Block Diagram

8.3 Feature Description

• Wide operating V_CC range of 0.8 V to 3.6 V
• 3.6-V I/O tolerant to support down translation
• Input hysteresis allows slow input transition and better switching noise immunity at the input
• I_off feature allows voltages on the inputs and outputs when V_CC is 0 V
• Low noise due to slower edge rates

8.4 Device Functional Modes

Table 1 shows the functional modes of the SN74AUP1G00 device.