SCES591J JULY 2004 – June 2014 SN74AUP1G07
PRODUCTION DATA.
- 1 Features
- 2 Applications
- 3 Description
- 4 Simplified Schematic
- 5 Revision History
- 6 Pin Configuration and Functions
-
7 Specifications
- 7.1 Absolute Maximum Ratings
- 7.2 Handling Ratings
- 7.3 Recommended Operating Conditions
- 7.4 Thermal Information
- 7.5 Electrical Characteristics
- 7.6 Switching Characteristics, CL = 5 pF
- 7.7 Switching Characteristics, CL = 10 pF
- 7.8 Switching Characteristics, CL = 15 pF
- 7.9 Switching Characteristics, CL = 30 pF
- 7.10 Operating Characteristics
- 7.11 Typical Characteristics
- 8 Parameter Measurement Information
- 9 Detailed Description
- 10Application and Implementation
- 11Power Supply Recommendations
- 12Layout
- 13Device and Documentation Support
- 14Mechanical, Packaging, and Orderable Information
12 Layout
12.1 Layout Guidelines
In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pins should not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. Figure 8 specifies the rules that must be observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should be applied to any particular unused input depends on the function of the device. Generally they will be tied to GND or VCC, whichever makes more sense or is more convenient. It is generally acceptable to float outputs, unless the part is a transceiver. If the transceiver has an output enable pin, it will disable the output section of the part when asserted. This will not disable the input section of the I/Os, so they cannot float when disabled.
12.2 Layout Example
Figure 8. Layout Diagram