米6体育平台手机版

SCES595N JULY 2004 – July 2017 SN74AUP1G125

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.

封装选项

机械数据 (封装 | 引脚)

DRY|6
- MPDS221F
DRL|5
- MPDS158F
DSF|6
- MPDS301G
DPW|5
- MPSS088
DCK|5
- MPDS025J
YZP|5
- MXBG018L
YFP|6
- MXBG056R
DBV|5
- MPDS018T

散热焊盘机械数据 (封装 | 引脚)

DRY|6
- QFND138E
DPW|5
- QFND567C

订购信息

8 Detailed Description

8.1 Overview

The AUP family is TI's premier solution to the industry's low-power needs in battery-powered portable applications. This family of devices is specified for low static and dynamic power consumption across the entire V_CC range of 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity (see Figure 2 and Figure 3).

The SN74AUP1G125 device contains one buffer gate device with output enable control and performs the Boolean function Y = A. This device is fully specified for partial-power-down applications using I_off . The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

To ensure the high-impedance state during power up or power down, OE must be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 Balanced High-Drive CMOS Push-Pull Outputs

A balanced output allows the device to sink and source similar currents. The high drive capability of this device creates fast edges into light loads so routing and load conditions should be considered to prevent ringing. Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without being damaged. It is important for the power output of the device to be limited to avoid thermal runaway and damage due to over-current. The electrical and thermal limits defined the in the Absolute Maximum Ratings must be followed at all times.

8.3.2 Standard CMOS Inputs

Standard CMOS inputs are high impedance and are typically modelled as a resistor in parallel with the input capacitance given in the Electrical Characteristics, TA = 25°C. The worst case resistance is calculated with the maximum input voltage, given in the Absolute Maximum Ratings, and the maximum input leakage current, given in the Electrical Characteristics, TA = 25°C, using ohm's law (R = V ÷ I).

Signals applied to the inputs need to have fast edge rates, as defined by Δt/Δv in Recommended Operating Conditions to avoid excessive currents and oscillations. If a slow or noisy input signal is required, a device with a Schmitt-trigger input should be utilized to condition the input signal prior to the standard CMOS input.

8.3.3 Clamp Diodes

The inputs and outputs to this device have negative clamping diodes.

CAUTION

Voltages beyond the values specified in the Absolute Maximum Ratings table can cause damage to the device. The input negative-voltage and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

SN74AUP1G125 SN74LVC1G79-ClampDiodes.gif

Figure 4. Electrical Placement of Clamping Diodes for Each Input and Output

8.3.4 Partial Power Down (I_off)

The inputs and outputs for this device enter a high impedance state when the supply voltage is 0 V. The maximum leakage into or out of any input or output pin on the device is specified by I_off in the Electrical Characteristics, TA = 25°C.

8.3.5 Over-voltage Tolerant Inputs

Input signals to this device can be driven above the supply voltage so long as they remain below the maximum input voltage value specified in the Absolute Maximum Ratings.

8.4 Device Functional Modes

Table 1 lists the functional modes for SN74AUP1G125.

Table 1. Function Table

INPUTS		OUTPUT
OE	A	Y
L	H	H
L	L	L
H	X	Hi-Z