米6体育平台手机版

SCES579J JUNE 2004 – September 2017 SN74AUP1G17

PRODUCTION DATA.

封装选项

机械数据 (封装 | 引脚)

DRY|6
- MPDS221F
DRL|5
- MPDS158F
DSF|6
- MPDS301G
DPW|5
- MPSS088
DCK|5
- MPDS025J
YZP|5
- MXBG018L
DBV|5
- MPDS018T
YFP|4
- MXBG055R

散热焊盘机械数据 (封装 | 引脚)

DRY|6
- QFND138E
DPW|5
- QFND567C

订购信息

8 Detailed Description

8.1 Overview

This device functions as an independent gate with Schmitt-trigger inputs, which allows for slow input transition and better switching-noise immunity at the input.

The AUP family is TI's premier solution to the industry's low power needs in battery-powered portable applications. This family assures a very low static and dynamic power consumption across the entire VCC range of 0.8 V to 3.6 V, resulting in an increased battery life.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs when the device is powered down. This inhibits current backflow into the device which prevents damage to the device and excess power consumption.

8.2 Functional Block Diagrams

Figure 5. Logic Diagram (Positive Logic)
(DBV, DCK, DPW, DRL, DRT, DRY, and YZP Packages)

Figure 6. Logic Diagram (Positive Logic)
(YFP Package)

8.3 Feature Description

8.3.1 Balanced High-Drive CMOS Push-Pull Outputs

A balanced output allows the device to sink and source similar currents. The high drive capability of this device creates fast edges into light loads so routing and load conditions should be considered to prevent ringing. Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without being damaged. It is important for the power output of the device to be limited to avoid thermal runaway and damage due to over-current. The electrical and thermal limits defined the in the Absolute Maximum Ratings table must be followed at all times.

8.3.2 Standard CMOS Inputs

Standard CMOS inputs are high impedance and are typically modelled as a resistor in parallel with the input capacitance given in the Electrical Characteristics table. The worst case resistance is calculated with the maximum input voltage, given in the Absolute Maximum Ratings table, and the maximum input leakage current, given in the Electrical Characteristics table, using ohm's law (R = V ÷ I).

Signals applied to the inputs need to have fast edge rates, as defined by Δt/Δv in Recommended Operating Conditions table to avoid excessive currents and oscillations. If a slow or noisy input signal is required, a device with a Schmitt-trigger input should be used to condition the input signal prior to the standard CMOS input.

8.3.3 Clamp Diodes

The inputs and outputs to this device have negative clamping diodes.

CAUTION

Voltages beyond the values specified in the Absolute Maximum Ratings table can cause damage to the device. The input negative-voltage and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

Figure 7. Electrical Placement of Clamping Diodes for Each Input and Output

8.3.4 Partial Power Down (I_off)

The inputs and outputs for this device enter a high impedance state when the supply voltage is 0 V. The maximum leakage into or out of any input or output pin on the device is specified by I_off in the Electrical Characteristics table.

8.3.5 Over-Voltage Tolerant Inputs

Input signals to this device can be driven above the supply voltage so long as they remain below the maximum input voltage value specified in the Absolute Maximum Ratings table.

8.4 Device Functional Modes

Table 1 lists the functional modes of the SN74AUP1G17 device.

Table 1. Function Table

INPUT A	OUTPUT Y
H	H
L	L