8.1 Overview

The AUP family is TI's premier solution to the low-power needs of the industry in battery-powered portable applications. This family ensures a very low static and dynamic power consumption across the entire V_CC range of 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity, which produces very low undershoot and overshoot characteristics.

The SN74AUP1G57 features configurable multiple functions. The output state is determined by eight patterns of 3-bit input. The user can choose the logic functions AND, OR, NAND, NOR, XNOR, inverter, and noninverter. All inputs can be connected to V_CC or GND.

The device functions as an independent gate with Schmitt-trigger inputs, which allow for slow input transition and better switching noise immunity at the input.

NanoStar package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

8.2 Functional Block Diagram

8.3 Feature Description

This part is available in the TI NanoStar package. It has low static-power consumption with I_CC = 0.9 μA maximum and low dynamic power consumption (C_pd = 4.3 pF, Typical at 3.3 V).

The inputs have low capacitance, with typical C_i = 1.5 pF.

This part has low noise, with overshoot and undershoot less than 10% of V_CC.

This part supports partial-power-down mode operation. When this part is powered down (V_CC = 0 V), the leakage current into the device is characterized by I_off.

Schmitt-trigger inputs provide hysterisis and consistency in V_IH / V_IL.

It has a wide operating V_CC range of 0.8 V to 3.6 V, and has been optimized for 3.3-V operation.

3.6-V I/O tolerant to support mixed-mode signal operation.

It has a low propagation delay of 5.3 ns at 3.3 V.

It is suitable for point-to-point applications.

8.4 Device Functional Modes

Table 1 lists all the functional modes of the SN74AUP1G57.

8.4.1 Logic Configurations

Table 2 lists all the logic functions of the SN74AUP1G57.

Table 2. Function Selection Table

LOGIC FUNCTION	FIGURE NO.
2-input AND	Figure 4
2-input AND with both inputs inverted	Figure 7
2-input NAND with inverted input	Figure 5, Figure 6
2-input OR with inverted input	Figure 5, Figure 6
2-input NOR	Figure 7
2-input NOR with both inputs inverted	Figure 4
2-input XNOR	Figure 8

Figure 4. 2-Input AND Gate

Figure 6. 2-Input NAND Gate With Inverted B Input

Figure 8. 2-Input XNOR Gate

Figure 5. 2-Input NAND Gate With Inverted A Input

Figure 7. 2-Input NOR Gate