ZHCSMG6E September   2009  – October 2021 SN74AUP2G07

PRODUCTION DATA  

  1. 特性
  2. 应用
  3. 说明
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Switching Characteristics, CL = 5 pF
    7. 6.7  Switching Characteristics, CL = 10 pF
    8. 6.8  Switching Characteristics, CL = 15 pF
    9. 6.9  Switching Characteristics, CL = 30 pF
    10. 6.10 Operating Characteristics
    11. 6.11 Typical Characteristics
  7. Parameter Measurement Information
    1. 7.1 Propagation Delays, Setup and Hold Times, and Pulse Duration
    2. 7.2 Enable and Disable Times
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 接收文档更新通知
    2. 12.2 支持资源
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 术语表
  13. 13Mechanical, Packaging, and Orderable Information

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Overview

The SN74AUP2G07 device is a dual buffer gate with open-drain outputs that operate from 0.8 V to 3.6 V. The output of this dual buffer/driver is open-drain, and can be connected to other open-drain outputs to implement active-low wired-OR or active-high wired-AND functions.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.The Ioff feature also allows for live insertion.