ZHCSX74M December   2003  – October 2024 SN74AVC2T45

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
    1.     Pin Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Switching Characteristics: VCCA = 1.2 V
    7. 5.7  Switching Characteristics: VCCA = 1.5 V ±0.1 V
    8. 5.8  Switching Characteristics: VCCA = 1.8 V ±0.15 V
    9. 5.9  Switching Characteristics: VCCA = 2.5 V ±0.2 V
    10. 5.10 Switching Characteristics: VCCA = 3.3 V ±0.3 V
    11. 5.11 Operating Characteristics
    12. 5.12 Typical Characteristics
      1. 5.12.1 Typical Propagation Delay (A to B) vs Load Capacitance, TA = 25°C, VCCA = 1.2 V
      2. 5.12.2 Typical Propagation Delay (A to B) vs Load Capacitance, TA = 25°C, VCCA = 1.5 V
      3. 5.12.3 Typical Propagation Delay (A-to-B) vs Load Capacitance, TA = 25°C, VCCA = 1.8 V
      4. 5.12.4 Typical Propagation Delay (A to B) vs Load Capacitance, TA = 25°C, VCCA = 2.5 V
      5. 5.12.5 Typical Propagation Delay (A to B) vs Load Capacitance, TA = 25°C, VCCA = 3.3 V
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 VCC Isolation
      2. 7.3.2 2-Rail Design
      3. 7.3.3 IO Ports are 4.6-V Tolerant
      4. 7.3.4 Partial-Power-Down Mode
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Unidirectional Logic Level-Shifting Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Bidirectional Logic Level-Shifting Application
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 Enable Times
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 接收文档更新通知
    3. 9.3 支持资源
    4. 9.4 Trademarks
    5. 9.5 静电放电警告
    6. 9.6 术语表
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • DCU|8
  • DDF|8
  • YZP|8
  • DCT|8
散热焊盘机械数据 (封装 | 引脚)
订购信息
8.2.2.2.1 Enable Times

Calculate the enable times for the SN74AVC2T45 using the following formulas:

  • tPZH (DIR to A) = tPLZ (DIR to B) + tPLH (B to A)
  • tPZL (DIR to A) = tPHZ (DIR to B) + tPHL (B to A)
  • tPZH (DIR to B) = tPLZ (DIR to A) + tPLH (A to B)
  • tPZL (DIR to B) = tPHZ (DIR to A) + tPHL (A to B)

In a bidirectional application, these enable times provide the maximum delay from the time the DIR bit is switched until an output is expected. For example, if the SN74AVC2T45 initially is transmitting from A to B, then the DIR bit is switched; the B port of the device must be disabled before presenting the device with an input. After the B port has been disabled, an input signal applied to the port appears on the corresponding A port after the specified propagation delay.
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