米6体育平台手机版

SCES908A February 2020 – April 2020 SN74AXC2T245-Q1

PRODUCTION DATA.

Unless otherwise noted, all input pulses are supplied by generators having the following characteristics:

1. C_L includes probe and jig capacitance.

Figure 1. Load Circuit

Table 1. Load Circuit Conditions

Parameter		V_CCO	R_L	C_L	S₁	V_TP
Δt/Δv	Input transition rise or fall rate	0.65 V – 3.6 V	1 MΩ	15 pF	Open	N/A
t_pd	Propagation (delay) time	1.1 V – 3.6 V	2 kΩ	15 pF	Open	N/A
t_pd	Propagation (delay) time	0.65 V – 0.95 V	20 kΩ	15 pF	Open	N/A
t_en, t_dis	Enable time, disable time	3 V – 3.6 V	2 kΩ	15 pF	2 × V_CCO	0.3 V
		1.65 V – 2.7 V	2 kΩ	15 pF	2 × V_CCO	0.15 V
		1.1 V – 1.6 V	2 kΩ	15 pF	2 × V_CCO	0.1 V
		0.65 V – 0.95 V	20 kΩ	15 pF	2 × V_CCO	0.1 V
t_en, t_dis	Enable time, disable time	3 V – 3.6 V	2 kΩ	15 pF	GND	0.3 V
		1.65 V – 2.7 V	2 kΩ	15 pF	GND	0.15 V
		1.1 V – 1.6 V	2 kΩ	15 pF	GND	0.1 V
		0.65 V – 0.95 V	20 kΩ	15 pF	GND	0.1 V

V_CCI is the supply pin associated with the input port.
V_OH and V_OL are typical output voltage levels that occur with specified R_L, C_L, and S₁

Figure 2. Propagation Delay

V_CCI is the supply pin associated with the input port.
V_OH and V_OL are typical output voltage levels that occur with specified R_L, C_L, and S₁

Figure 3. Input Transition Rise or Fall Rate

1. Output waveform on the condition that input is driven to a valid Logic Low.

2. Output waveform on the condition that input is driven to a valid Logic High.

3. V_CCO is the supply pin associated with the output port.

4. V_OH and V_OL are typical output voltage levels with specified R_L, C_L, and S₁.

Figure 4. Enable Time And Disable Time