ZHCSJ32C December 2018 – September 2020 SN74AXCH1T45
PRODUCTION DATA
- 1 特性
- 2 应用
- 3 说明
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Parameter Measurement Information
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Feature Description
- 8.3.1 Standard CMOS Inputs
- 8.3.2 Balanced High-Drive CMOS Push-Pull Outputs
- 8.3.3 Partial Power Down (Ioff)
- 8.3.4 VCC Isolation
- 8.3.5 Over-voltage Tolerant Inputs
- 8.3.6 Negative Clamping Diodes
- 8.3.7 Fully Configurable Dual-Rail Design
- 8.3.8 Supports High-Speed Translation
- 8.3.9 Bus-Hold Data Inputs
- 8.4 Device Functional Modes
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
封装选项
机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
- DRY|6
订购信息
9.2.2 Universal Asynchronous Receiver-Transmitter (UART) Interface Application
Figure 9-3 shows the SN74AXCH1T45 being used for the two-bit UART interface application. One SN74AXCH1T45 device is used to level shift the voltage and drive the TX from the processor to the GPS Module while a second SN74AXCH1T45 device is used to drive the TX Data line from the GPS Module to the Processor. Devices with bus-hold inputs remove the requirement for external pullup resistors to maintain a valid logic level at the input.
Figure 9-3 UART Interface Application