1 Features

• High-Bandwidth Data Path (Up to 500 MHz)⁽¹⁾⁽¹⁾
• 5-V Tolerant I/Os With Device Powered Up or Powered Down
• Low and Flat ON-State Resistance (r_on) Characteristics Over Operating Range
  (r_on= 5 Ω Typical)
• Rail-to-Rail Switching on Data I/O Ports
  • 0 to 5-V Switching With 3.3-V V_CC
  • 0 to 3.3-V Switching With 2.5-V V_CC
• Bidirectional Data Flow With Near-Zero Propagation Delay
• Low Input and Output Capacitance Minimizes Loading and Signal Distortion
  (C_io(OFF) = 4 pF Typical)
• Fast Switching Frequency (f_OE = 20 MHz Maximum)
• Data and Control Inputs Provide Undershoot Clamp Diodes
• Low Power Consumption (I_CC = 1 mA Typical)
• V_CC Operating Range From 2.3 V to 3.6 V
• Data I/Os Support 0 to 5-V Signaling Levels
  (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V, 5 V)
• Control Inputs Can Be Driven by TTL or
  5-V and 3.3-V CMOS Outputs
• I_off Supports Partial-Power-Down Mode Operation
• Latch-Up Performance Exceeds 100 mA
  Per JESD 78, Class II
• ESD Performance Tested Per JESD 22
  • 2000-V Human Body Model
    (A114-B, Class II)
  • 1000-V Charged-Device Model (C101)
• Supports Both Digital and Analog Applications ⁽¹⁾

2 Applications

• IP Phones: Wired and Wireless
• Optical Modules
• Optical Networking: Video Over Fiber and EPON
• Private Branch Exchange (PBX)
• WiMAX and Wireless Infrastructure Equipment

3 Description

The SN74CB3Q16244 device is a high-bandwidth FET bus switch using a charge pump to elevate the gate voltage of the pass transistor, providing a low and flat ON-state resistance (r_on). The low and flat ON-state resistance allows for minimal propagation delay and supports rail-to-rail switching on the data input/output (I/O) ports. The SN74CB3Q16244 device also features low data I/O capacitance to minimize capacitive loading and signal distortion on the data bus. Specifically designed to support high-bandwidth applications, the SN74CB3Q16244 device provides an optimized interface solution ideally suited for broadband communications, networking, and data-intensive computing systems.

1. For all available packages, see the orderable addendum at the end of the data sheet.

Logic Diagram (Positive Logic)

4 Revision History

Changes from A Revision (March 2005) to B Revision

• Added Applications, Device Information table, Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section Go
• Removed Ordering Information table. Go