Standard CMOS inputs are high impedance and are typically modeled as a resistor from the input to ground in parallel with the input capacitance given in the GUID-3ABB105B-A680-4E29-8298-466CC52D7528.html#GUID-3ABB105B-A680-4E29-8298-466CC52D7528. The worst case resistance is calculated with the maximum input voltage, given in the GUID-2065CE0D-C62C-4275-9B9F-9360393448B5.html#GUID-2065CE0D-C62C-4275-9B9F-9360393448B5, and the maximum input leakage current, given in the GUID-3ABB105B-A680-4E29-8298-466CC52D7528.html#GUID-3ABB105B-A680-4E29-8298-466CC52D7528, using ohm's law (R = V ÷ I).

Signals applied to the inputs need to have fast edge rates, as defined by the input transition time in the GUID-21AD65E0-3428-4493-BB6D-29EA624FF219.html#GUID-21AD65E0-3428-4493-BB6D-29EA624FF219 to avoid excessive current consumption and oscillations. If a slow or noisy input signal is required, a device with a Schmitt-trigger input should be used to condition the input signal prior to the standard CMOS input.