The SN74HCS137-Q1 is a high speed silicon gate CMOS decoder well suited to memory address decoding or data routing applications. It contains a single 3:8 decoder. All inputs include Schmitt-triggers allowing for slow input transitions and providing additional noise margin.

The SN74HCS137-Q1 has three address select inputs (A₂, A₁, and A₀). When the latch enable (LE) input is low, the circuit functions as a normal one-of-eight decoder. When the latch enable (LE) input is high, the address latches will maintain their previous states, regardless of any changes at the address select inputs.

Two strobe inputs (G₁ and G₀) are provided to simplify cascading and to facilitate demultiplexing. When any input strobe is active, all outputs are forced into the high state.

The demultiplexing function is accomplished by first using the select inputs to choose the desired output, and then using one of the strobe inputs as the data input.

The outputs for the SN74HCS137-Q1 are normally high, and low when selected.