The SN74HCS164-Q1 is an 8-bit shift register with 2 serial inputs (A and B) connected through an AND gate, as well as an asynchronous clear (CLR). The device requires a high signal on both A and B in order to set the input data line high; a low signal on either input will set the input data line low. Data at A and B can be changed while CLK is high or low, provided that the minimum set-up time requirements are met.

The CLK pin of the SN74HCS164-Q1 is rising-edge triggered, activating on the transition from LOW to HIGH. Upon a positive-edge trigger, the device will store the result of the (A ● B) input data line in the first register and propagate each register’s data to the next register. The data of the last register, Q_H, will be discarded at each clock trigger. If a low signal is applied to the CLR pin, then the SN74HCS164-Q1 will set all registers to a logical low value immediately.