ZHCSP60A November 2021 – February 2022 SN74HCS240-Q1
PRODUCTION DATA
The SN74HCS240-Q1 contains 8 individual high speed CMOS inverters with Schmitt-trigger inputs and 3-state outputs.
Each inverter performs the boolean logic function xYn = xAn, with x being the bank number and n being the channel number.
Each output enable (xOE) controls four inverters. When the xOE pin is in the low state, the outputs of all inverters in the bank x are enabled. When the xOE pin is in the high state, the outputs of all inverters in the bank x are disabled. All disabled output are placed into the high-impedance state.
To ensure the high-impedance state during power up or power down, both OE pins should be tied to VCC through a pull-up resistor; the minimum value of the resistor is determined by the current sinking capability of the driver and the leakage of the pin as defined in the Electrical Characteristics table.