The SN74HCS273 contains 8 positive-edge-triggered D-type flip-flops with shared direct active low clear (CLR) input.

Information at the data (D) inputs meeting the setup time requirements is transferred to the (Q) outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not related directly to the transition time of the positive-going pulse. When CLK is at either the high or low level or transitioning from a high level to a low level, the D input has no effect at the output.

Information at the data (Q) outputs can be asychronously cleared with a low level input through the clear (CLR) pin.