The SN74HCS365-Q1 hex buffers and line drivers are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The SN74HCS365-Q1 devices contain six independent buffers/drivers with dual-gated output-enable (OE1 and OE2) inputs. When OE1 and OE2 are both low, each channel passes noninverted data from the A input to the Y output. If either (or both) output-enable terminal(s) is high, the outputs are in the high-impedance state.