ZHCSO37A October   2020  – May 2021 SN74HCS594

PRODUCTION DATA  

  1. 特性
  2. 应用
  3. 说明
    1.     4
    2.     5
  4. Revision History
  5. Pin Configuration and Functions
    1.     8
    2.     9
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Characteristics
    7. 6.7 Switching Characteristics
    8. 6.8 Operating Characteristics
    9. 6.9 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Balanced CMOS Push-Pull Outputs
      2. 8.3.2 CMOS Schmitt-Trigger Inputs
      3. 8.3.3 Clamp Diode Structure
    4. 8.4 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Power Considerations
        2. 9.2.1.2 Input Considerations
        3. 9.2.1.3 Output Considerations
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 接收文档更新通知
    3. 12.3 支持资源
    4. 12.4 Trademarks
    5. 12.5 静电放电警告
    6. 12.6 术语表
  13. 13Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

Timing Characteristics

CL = 50 pF; over operating free-air temperature range (unless otherwise noted). See Parameter Measurement Information.
PARAMETER VCC Operating free-air temperature (TA) UNIT
25°C –40°C to 125°C
MIN MAX MIN MAX
fclock Clock frequency 2 V 32 17
4.5 V 100 54
6 V 115 68
tw Pulse duration SRCLK or RCLK high or low 2 V 8 12 ns
4.5 V 6 7
6 V 6 7
SRCLR or RCLR low 2 V 7 12
4.5 V 6 7
6 V 6 7

tsu
 

Setup time

SER before SRCLK↑ 2 V 11 16 ns
4.5 V 4 7
6 V 4 5
SRCLK↑ before RCLK↑ 2 V 15 24
4.5 V 5 9
6 V 5 7
SRCLR low before RCLK↑ 2 V 16 27
4.5 V 7 10
6 V 5 8
SRCLR high (inactive) before SRCLK↑ 2 V 5 9
4.5 V 3 5
6 V 3 4
RCLR high (inactive) before RCLK↑ 2 V 8 12
4.5 V 4 5
6 V 3 4

th
 

Hold time

SER after SRCLK↑ 2 V 0 0 ns
4.5 V 0 0
6 V 0 0