ZHCSP29A October   2021  – December 2021 SN74HCT595

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Characteristics
    7. 6.7 Switching Characteristics
    8.     14
    9. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Functional Block Diagram
    2. 8.2 Feature Description
      1. 8.2.1 Balanced CMOS 3-State Outputs
      2. 8.2.2 Balanced CMOS Push-Pull Outputs
      3. 8.2.3 TTL-Compatible CMOS Inputs
      4. 8.2.4 Latching Logic
      5. 8.2.5 Clamp Diode Structure
    3. 8.3 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Power Considerations
        2. 9.2.1.2 Input Considerations
        3. 9.2.1.3 Output Considerations
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 接收文档更新通知
    3. 12.3 支持资源
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 术语表
  13. 13Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6.6 Timing Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER CONDITION VCC TA = 25°C -40°C to 125°C UNIT
MIN MAX MIN MAX
fclock Clock frequency 4.5 V 31 25 MHz
tw Pulse duration SRCLK or RCLK high or low 4.5 V 16 20 ns
5.5 V 16 20
SRCLR low 4.5 V 16 20
5.5 V 16 20
tsu Setup time SER before SRCLK↑ 4.5 V 20 25 ns
5.5 V 20 25
SRCLK↑ before RCLK↑ 4.5 V 16 20
5.5 V 16 20
SRCLR low before RCLK↑ 4.5 V 10 13
5.5 V 10 13
SRCLR high (inactive) before SRCLK↑ 4.5 V 10 12
5.5 V 10 12
th Hold time SER after SRCLK↑ 4.5 V 0 0 ns
5.5 V 0 0
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