8.1 Overview

Functional Block Diagram shows that the count modulo is controlled by an X/Y decoder connected to the mode control inputs of several flip-flops. These flip-flops with mode controls each have a D input connected to the parallel clock line, and a T input driven by the preceding stage. The parallel clock frequency is always the input frequency divided by four.

The X/Y decoder output selected by the programming inputs goes low. While a mode control is slow, the D input of that flip-flop is enabled, and the signal from the parallel clock line (f_in ÷ 4) is passed to the T input of the following stage. All the other mode controls are high, enabling the T inputs and causing each flip-flop in turn to divide by two.

8.2 Functional Block Diagram

8.3 Feature Description

This SN74LS29x device can be used to digitally program from 2² to 2ⁿ (n = 31 for SN74LS292, n = 15 for SN74LS294) divider chain. This has a useable frequency range up to 30 MHz. The flexibility is offered when the devices are cascaded to have desired timing delay.

8.4 Device Functional Modes

Table 1, Table 2, and Table 3 list the functional modes of the SN74LS292.

Figure 7, Figure 9, and Figure 9 show the schematics of inputs and outputs of the SN74LS292.

Figure 7. Equivalent of Each Input

Figure 8. Typical of Q Outputs

Figure 9. Typical of TP Outputs