SDLS153A January   1981  – January 2016 SN74LS292 , SN74LS294

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Recommended Operating Conditions
    3. 6.3 Thermal Information
    4. 6.4 Electrical Characteristics
    5. 6.5 Switching Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Logic Diagrams
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

5 Pin Configuration and Functions

SN74LS29x J, W, or N Package
16-Pin PDIP
Top View
SN74LS292 SN74LS294 pinout_01_SDLS153.gif

Pin Functions, SN74LS292

PIN I/O DESCRIPTION
NAME PDIP
A 10 I Programming input A
B 1 I Programming input B
C 15 I Programming input C
CLK1 4 I Clock 1 input
CLK2 5 I Clock 2 input
CLR 11 I Active-low clear input
D 14 I Programming input D
E 2 I Programming input E
GND 8 - Ground
NC 9, 12 - No connect
Q 7 O Q Output
TP — O Test Point
TP1 3 O Test Point
TP2 6 O Test Point
TP3 13 O Test Point
VCC 16 - Power

Pin Functions, SN74LS294

PIN I/O DESCRIPTION
NAME PDIP
A 2 I Programming input A
B 1 I Programming input B
C 15 I Programming input C
CLK1 4 I Clock 1 input
CLK2 5 I Clock 2 input
CLR 11 I Active-low clear input
D 14 I Programming input D
E — I Programming input E
GND 8 - Ground
NC 6, 9 ,10, 12, 13 - No connect
Q 7 O Q Output
TP 3 O Test Point
TP1 — O Test Point
TP2 — O Test Point
TP3 — O Test Point
VCC 16 - Power
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