SCLS467F FEBRUARY   2003  – June 2016 SN74LV123A-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements — VCC = 3.3 V ± 0.3 V
    7. 6.7  Timing Requirements — VCC = 5 V ± 0.5 V
    8. 6.8  Switching Characteristics — VCC = 3.3 V ± 0.3 V
    9. 6.9  Switching Characteristics — VCC = 5 V ± 0.5 V
    10. 6.10 Operating Characteristics
    11. 6.11 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power-Down Considerations
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Output Pulse Duration
        2. 9.2.1.2 Retriggering Data
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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机械数据 (封装 | 引脚)
  • PW|16
散热焊盘机械数据 (封装 | 引脚)
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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature (unless otherwise noted)(1)
MIN MAX UNIT
Supply voltage, VCC –0.5 7 V
Input voltage, VI(2) –0.5 7 V
Voltage range applied to any output in the high-impedance or power-off state, VO(2) –0.5 7 V
Output voltage, VO VO In the high or low state(3)(2) –0.5 VCC + 0.5 V
In the power-off state, VO(2) –0.5 7 V
Input clamp current, IIK VI < 0 –20 mA
Output clamp current, IOK VO < 0 –50 mA
Continuous output current, IO VO = 0 to VCC ±25 mA
Continuous current through VCC or GND ±50 mA
Operating virtual junction temperature, TJ 150 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(3) The value is limited to 5.5 V maximum.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage 2 5.5 V
VIH High-level input voltage VCC = 2 V 1.5 V
VCC = 2.3 V to 2.7 V VCC × 0.7
VCC = 3 V to 3.6 V VCC × 0.7
VCC = 4.5 V to 5.5 V VCC × 0.7
VIL Low-level input voltage VCC = 2 V 0.5 V
VCC = 2.3 V to 2.7 V VCC × 0.3
VCC = 3 V to 3.6 V VCC × 0.3
VCC = 4.5 V to 5.5 V VCC × 0.3
VI Input voltage 0 5.5 V
VO Output voltage 0 VCC V
IOH High-level output current VCC = 2 V –50 μA
VCC = 2.3 V to 2.7 V –2 mA
VCC = 3 V to 3.6 V –6
VCC = 4.5 V to 5.5 V –12
IOL Low-level output current VCC = 2 V 50 μA
VCC = 2.3 V to 2.7 V 2 mA
VCC = 3 V to 3.6 V 6
VCC = 4.5 V to 5.5 V 12
Rext External timing resistance VCC = 2 V 5 kΩ
VCC ≥ 3 V 1
Cext External timing capacitance No restriction pF
Δt/ΔVCC Power-up ramp rate 1 ms/V
TA Operating free-air temperature –40 125 °C
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, SCBA004.

6.4 Thermal Information

THERMAL METRIC(1) SN74LV123A-Q1 UNIT
PW (TSSOP)
16 PINS
RθJA Junction-to-ambient thermal resistance 111.2 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 46.1 °C/W
RθJB Junction-to-board thermal resistance 56.3 °C/W
ψJT Junction-to-top characterization parameter 5.6 °C/W
ψJB Junction-to-board characterization parameter 55.7 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance n/a °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
VOH High-level output voltage IOH = –50 μA 2 V to 5.5 V 0.1 V
IOH = –2 mA 2.3 V 2
IOH = –6 mA 3 V 2.48
IOH = –12 mA 4.5 V 3.8
VOL Low-level output voltage IOL = 50 μA 2 V to 5.5 V 0.1 V
IOL = 2 mA 2.3 V 0.4
IOL = 6 mA 3 V 0.44
IOL = 12 mA 4.5 V 0.55
II Input current Rext/Cext(1) VI = 5.5 V or GND 5.5 V ±2.5 μA
A, B, and CLR VI = 5.5 V or GND 0 V ±1
0 to 5.5 V ±1
ICC Quiescent current VI = VCC or GND, IO = 0 5.5 V 20 μA
ICC Supply current, Active state (per circuit) VI = VCC or GND, Rext/Cext = 0.5 VCC 3 V 280 μA
4.5 V 650
5.5 V 975
Ioff Off-state current VI or VO = 0 to 5.5 V 0 V 5 μA
Ci Input capacitance VI = VCC or GND 3.3 V 1.9 pF
5 V 1.9
(1) This test is performed with the terminal in the off-state condition.

6.6 Timing Requirements — VCC = 3.3 V ± 0.3 V

over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted). See Figure 1 and the circuits in the Parameter Measurement Information section.
MIN NOM(2) MAX UNIT
tw Pulse duration CLR 5  ns
A or B trigger 5 
trr Pulse retrigger time, Rext = 1 kΩ Cext = 100 pF See(1)  76 ns
Cext = 0.01 μF See(1)  1.8 μs
(1) See retriggering data in the Application and Implementation section.
(2) TA = 25°C

6.7 Timing Requirements — VCC = 5 V ± 0.5 V

over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted). See Figure 1 and the circuits in the Parameter Measurement Information section.
MIN NOM(2) MAX UNIT
tw Pulse duration CLR 5  ns
A or B trigger 5 
trr Pulse retrigger time, Rext = 1 kΩ Cext = 100 pF See(1)  59 ns
Cext = 0.01 μF See(1)  1.5 μs
(1) See retriggering data in the Application and Implementation section
(2) TA = 25°C

6.8 Switching Characteristics — VCC = 3.3 V ± 0.3 V

over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted). See the circuits in the Parameter Measurement Information section.
PARAMETER FROM
(INPUT)		 TO
(OUTPUT)		 TEST
CONDITIONS		 TA = 25°C TA = –40 to +125°C UNIT
MIN TYP MAX MIN MAX
tpd Propagation delay A or B Q or Q CL = 50 pF 11.8 24.1 1 27.5 ns
CLR Q or Q 10.5 19.3 1 22
CLR trigger Q or Q 12.3 25.9 1 29.5
tw Duration of pulse at Q and Q outputs Q or Q CL = 50 pF
Cext = 28 pF
Rext = 2 kΩ		 182 240 300 ns
CL = 50 pF
Cext = 0.01 μF
Rext = 10 kΩ		 90 100 110 90 110 μs
CL = 50 pF
Cext = 0.1 μF
Rext = 10 kΩ		 0.9 1 1.1 0.9 1.1 ms
Δtw Output pulse-duration variation (Q and Q) between circuits in same package CL = 50 pF ±1%

6.9 Switching Characteristics — VCC = 5 V ± 0.5 V

over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted). See the circuits in the Parameter Measurement Information section.
PARAMETER FROM
(INPUT)		 TO
(OUTPUT)		 TEST
CONDITIONS		 TA = 25°C TA = –40 to +125°C UNIT
MIN TYP MAX MIN MAX
tpd Propagation delay A or B Q or Q CL = 50 pF 8.3 14 1 16 ns
CLR Q or Q 7.4 11.4 1 13
CLR trigger Q or Q 8.7 14.9 1 17
tw Duration of pulse at Q and Q outputs Q or Q CL = 50 pF
Cext = 28 pF
Rext = 2 kΩ		 167 200 240 ns
CL = 50 pF
Cext = 0.01 μF
Rext = 10 kΩ		 90 100 110 90 110 μs
CL = 50 pF
Cext = 0.1 μF
Rext = 10 kΩ		 0.9 1 1.1 0.9 1.1 ms
Δtw Output pulse-duration variation (Q and Q) between circuits in same package CL = 50 pF ±1%

6.10 Operating Characteristics

TA = 25°C
PARAMETER TEST CONDITIONS VCC TYP UNIT
Cpd Power dissipation capacitance CL = 50 pF, f = 10 MHz 3.3 V 44 pF
5 V 49
SN74LV123A-Q1 timing_cls467.gif Figure 1. Input and Output (I/O) Timing Diagram

6.11 Typical Characteristics

Operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied.
SN74LV123A-Q1 app1_cls467.gif
VCC = 3 V TA = 25 °C
Figure 2. Output Pulse Duration (tw) vs External Timing Capacitance (CT)
SN74LV123A-Q1 app3_cls467.gif
RT = 1 kΩ TA = 25 °C
Figure 4. Minimum Trigger Time (trr) vs VCC Characteristics
SN74LV123A-Q1 app2_cls467.gif
VCC = 4.5 V TA = 25 °C
Figure 3. Output Pulse Duration vs External Timing Capacitance
SN74LV123A-Q1 app4_cls467.gif
RT = 1 kΩ TA = 25 °C tw = K × CT × RT
Figure 5. Output Pulse-Duration Constant vs Supply Voltage
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