SCLS393Q APRIL 1998 – August 2015 SN74LV123A
UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.
- 1 Features
- 2 Applications
- 3 Description
- 4 Revision History
- 5 Description (continued)
- 6 Pin Configuration and Functions
-
7 Specifications
- 7.1 Absolute Maximum Ratings
- 7.2 ESD Ratings
- 7.3 Recommended Operating Conditions
- 7.4 Thermal Information
- 7.5 Electrical Characteristics
- 7.6 Timing Requirements, VCC = 2.5 V ± 0.2 V
- 7.7 Timing Requirements, VCC = 3.3 V ± 0.3 V
- 7.8 Timing Requirements, VCC = 5 V ± 0.5 V
- 7.9 Switching Characteristics, VCC = 2.5 V ± 0.2 V
- 7.10 Switching Characteristics, VCC = 3.3 V ± 0.3 V
- 7.11 Switching Characteristics, VCC = 5 V ± 0.5 V
- 7.12 Operating Characteristics
- 7.13 Typical Characteristics
- 8 Parameter Measurement Information
- 9 Detailed Description
- 10Application and Implementation
- 11Power Supply Recommendations
- 12Layout
- 13Device and Documentation Support
- 14Mechanical, Packaging, and Orderable Information
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12 Layout
12.1 Layout Guidelines
When using multiple bit logic devices, inputs must never float. In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two inputs of a triple-input AND gate are used or only three of the four buffer gates are used. Such input pins must not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that must be applied to any particular unused input depends on the function of the device. Generally they will be tied to GND or VCC whichever makes more sense or is more convenient. Floating outputs is generally acceptable, unless the part is a transceiver.
12.2 Layout Example
Figure 16. Layout Recommendation
Figure 17. Trace Example