The SN74LV165A-Q1 device is a parallel-load, 8-bit shift registers designed for 2 V to 5.5 V V_CC operation.

When the device is clocked, data is shifted toward the serial output Q_H. Parallel-in access to each stage is provided by eight individual direct data inputs that are enabled by a low level at the shift/load (SH/ LD) input. The SN74LV165A-Q1 features a clock-inhibit function and a complemented serial output, Q_H.

Clocking is accomplished by a low-to-high transition of the clock (CLK) input while SH/ LD is held high and clock inhibit (CLK INH) is held low. The functions of CLK and CLK INH are interchangeable. Since a low CLK and a low-to-high transition of CLK INH accomplishes clocking, CLK INH must be changed to the high level only while CLK is high. Parallel loading is inhibited when SH/ LD is held high. The parallel inputs to the register are enabled while SH/ LD is held low, independently of the levels of CLK, CLK INH, or SER.

The SN74LV165A-Q1 is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.