Add a decoupling capacitor from
VCC to GND. The capacitor needs to be placed physically close to
the device and electrically close to both the VCC and GND pins. An
example layout is shown in the Layout section.
Ensure the capacitive load at the
output is ≤ 50 pF. This is not a hard limit; by design, however, it will
optimize performance. This can be accomplished by providing short, appropriately
sized traces from the SN74LV1T86-Q1 to one or more of
the receiving devices.
Ensure the resistive load at the
output is larger than (VCC / IO(max)) Ω. Doing this will
not violate the maximum output current from the Absolute Maximum Ratings.
Most CMOS inputs have a resistive load measured in MΩ; much larger than the
minimum calculated previously.
Thermal issues are rarely a
concern for logic gates; the power consumption and thermal increase, however,
can be calculated using the steps provided in the application report, CMOS
Power Consumption and Cpd Calculation.