The SN74LV373A device is an octal transparent D-type latch designed for 2 V to 5.5 V V_CC operation.

When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs.

At power-up, the state of the Q outputs are not predictable until the first valid clock.

A buffered output-enable ( OE) input can be used to place the eight outputs in either a normal logic state (high or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pull-up components.

OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE should be tied to V_CC through a pull-up resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.