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SCES656E February 2006 – November 2016 SN74LV4046A

PRODUCTION DATA.

封装选项

机械数据 (封装 | 引脚)

DGV|16
- MPDS006C
N|16
- MPDI002C
PW|16
- MPDS361A
D|16
- MPDS178G
NS|16
- MPDS551A

散热焊盘机械数据 (封装 | 引脚)

订购信息

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

			MIN	MAX	UNIT
V_CC	DC supply voltage		–0.5	7	V
V_I	Input voltage		–0.5	V_CC + 0.5	V
V_O	Output voltage		–0.5	V_CC + 0.5	V
I_IK	Input clamp current	V_I < 0		–20	mA
I_OK	Output clamp current	V_O < 0		–50	mA
I_O	Continuous output curent	V_O= 0 to V_CC		±35	mA
I_CC	DC V_CC or ground current			±70	mA
T_J	Junction temperature			150	°C
T_stg	Storage temperature		–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±1000	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	MAX	UNIT
T_A	Operating free-air temperature	–40	125	°C
V_CC	Supply voltage	3	5.5	V
V_I, V_O	DC input or output voltage	0	V_CC	V

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		SN74LV4046A					UNIT
		D (SOIC)	DGV (TVSOP)	NS (SO)	PW (TSSOP)	N (PDIP)
		16 PINS	16 PINS	16 PINS	16 PINS	16 PINS
R_θJA	Junction-to-ambient thermal resistance	82.8	116.8	83.5	108.1	49.4	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	44.0	43.3	41.7	42.7	36.7	°C/W
R_θJB	Junction-to-board thermal resistance	40.3	48.3	43.8	53.1	29.3	°C/W
ψ_JT	Junction-to-top characterization parameter	11.1	3.7	9.3	4.2	21.5	°C/W
ψ_JB	Junction-to-board characterization parameter	40.0	47.8	43.5	52.5	29.2	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER				TEST CONDITIONS		V_CC (V)	MIN	TYP	MAX	UNIT
PARAMETER				V_I (V)	I_O (mA)	V_CC (V)	MIN	TYP	MAX	UNIT
VCO
V_IH	High-level input voltage	INH				3 to 3.6	V_CC × 0.7			V
V_IH	High-level input voltage	INH				4.5 to 5.5	V_CC × 0.7			V
V_IL	Low-level input voltage	INH				3 to 5.5			V_CC × 0.3	V
V_IL	Low-level input voltage	INH				4.5 to 5.5			V_CC × 0.3	V
V_OH	High-level output voltage	VCO_OUT	CMOS	V_IL or V_IH	–0.05	3 to 3.6	V_CC – 0.1			V
			CMOS		–0.05	4.5 to 5.5	V_CC – 0.1
			TTL		–12	4.5 to 5.5	3.8
V_OL	Low-level output voltage	VCO_OUT	CMOS	V_IL or V_IH	0.05	3 to 3.6			0.1	V
			CMOS		0.05	4.5 to 5.5			0.1
			TTL		12	4.5 to 5.5			0.55
		C1A, C1B (test purposes only)			12	4.5 to 5.5			0.65
I_I	Input leakage current	INH, VCO_IN		V_CC or GND		5.5			±1	μA
	R1 range⁽¹⁾					3 to 5.5	3		50	kΩ
	R2 range⁽¹⁾					3 to 5.5	3		50	kΩ
	C1 capacitance range					3 to 3.6	40		No Limit	pF
	C1 capacitance range					4.5 to 5.5	40		No Limit	pF
	Operating voltage range	VCO_IN		Over the range specified for R1 for linearity⁽²⁾		3 to 3.6	1.1		1.9	V
	Operating voltage range	VCO_IN		Over the range specified for R1 for linearity⁽²⁾		4.5 to 5.5	1.1		3.2	V
PHASE COMPARATOR
V_IH	DC-coupled high-level input voltage		SIG_IN, COMP_IN			3 to 3.6	V_CC × 0.7
V_IH	DC-coupled high-level input voltage		SIG_IN, COMP_IN			4.5 to 5.5	V_CC × 0.7
V_IL	DC-coupled low-level input voltage		SIG_IN, COMP_IN			3 to 3.6			V_CC × 0.3	V
V_IL	DC-coupled low-level input voltage		SIG_IN, COMP_IN			4.5 to 5.5			V_CC × 0.3	V
V_OH	High-level output voltage	PCP_OUT, PCN_OUT	CMOS	V_IL or V_IH	–0.05	3 to 5.5	V_CC – 0.1			V
			CMOS		–6	3 to 3.6	2.48
			TTL		–12	4.5 to 5.5	3.8
V_OL	Low-level output voltage	PCP_OUT, PCN_OUT	CMOS	V_IL or V_IH	0.02	3 to 3.6			0.1	V
					0.02	4.5 to 5.5			0.1
					4	4.5 to 5.5			0.4
			TTL		4	4.5 to 5.5			0.4
I_I	Input leakage current		SIG_IN, COMP_IN	V_CC or GND		3 to 3.6			±11	μA
I_I	Input leakage current		SIG_IN, COMP_IN	V_CC or GND		4.5 to 5.5			±29	μA
I_OZ	3-state off-state current		PC2_OUT	V_IL or V_IH		3 to 5.5			±5	μA
R_I	Input resistance		SIG_IN, COMP_IN	V_I at self-bias operating point, V_I = 0.5 V		3		800		kΩ
R_I	Input resistance		SIG_IN, COMP_IN	V_I at self-bias operating point, V_I = 0.5 V		4.5		250		kΩ
DEMODULATOR
R_S	Resistor range			R_S > 300 kΩ, Leakage current can influence V_DEMOUT		3 to 3.6	50		300	kΩ
R_S	Resistor range			R_S > 300 kΩ, Leakage current can influence V_DEMOUT		4.5 to 5.5	50		300	kΩ
V_OFF	Offset voltage VCO_IN to V_DEM			V_I = V_VCOIN = V_CC/2, Values taken over R_S range		3 to 3.6		±30		mV
V_OFF	Offset voltage VCO_IN to V_DEM			V_I = V_VCOIN = V_CC/2, Values taken over R_S range		4.5 to 5.5		±20		mV
I_CC	Quiescent device current			Pins 3, 5, and 14 at V_CC, Pin 9 at GND, I_I at pins 3 and 14 to be excluded		5.5			50	μA

(1) The value for R1 and R2 in parallel should exceed 2.7 kΩ.

(2) The maximum operating voltage can be as high as V_CC – 0.9 V; however, this may result in an increased offset voltage.

6.6 Switching Characteristics

over operating free-air temperature range (unless otherwise noted) C_L = 50 pF, Input t_r, t_f= 6 ns

PARAMETER			TEST CONDITIONS	V_CC (V)	MIN	TYP	MAX	UNIT
PHASE COMPARATOR
t_PLH, t_PHL	Propagation delay	SIG_IN, COMP_IN to PC1_OUT		3 to 3.6			135	ns
t_PLH, t_PHL	Propagation delay	SIG_IN, COMP_IN to PC1_OUT		4.5 to 5.5			50	ns
t_PLH, t_PHL	Propagation delay	SIGIN, COMP_IN to PCP_OUT		3 to 3.6			300	ns
t_PLH, t_PHL	Propagation delay	SIGIN, COMP_IN to PCP_OUT		4.5 to 5.5			60	ns
t_PLH, t_PHL	Propagation delay	SIG_IN, COMP_IN to PC3_OUT		3 to 3.6			200	ns
t_PLH, t_PHL	Propagation delay	SIG_IN, COMP_IN to PC3_OUT		4.5 to 5.5			50	ns
t_THL, t_TLH	Output transition time			3 to 3.6			75	ns
t_THL, t_TLH	Output transition time			4.5 to 5.5			15	ns
t_PZH, t_PZL	3-state output enable time	SIG_IN, COMP_IN to PC2_OUT		3 to 3.6			270	ns
t_PZH, t_PZL	3-state output enable time	SIG_IN, COMP_IN to PC2_OUT		4.5 to 5.5			54	ns
t_PHZ, t_PLZ	3-state output disable time	SIG_IN, COMP_IN to PC2OUT		3 to 3.6			320	ns
t_PHZ, t_PLZ	3-state output disable time	SIG_IN, COMP_IN to PC2OUT		4.5 to 5.5			65	ns
	AC-coupled input sensitivity	(P-P) at SIG_IN or COMP_IN	V_I(P-P)	3 to 3.6		11		mV
	AC-coupled input sensitivity	(P-P) at SIG_IN or COMP_IN	V_I(P-P)	4.5 to 5.5		15		mV
VCO
Δf/ΔT	Frequency stability with temperature change		V_I = VCO_IN = 1/2 V_CC, R₁ = 100 kΩ, R₂ = ∞, C₁ = 100 pF	3 to 3.6		0.11		%/°C
Δf/ΔT	Frequency stability with temperature change		V_I = VCO_IN = 1/2 V_CC, R₁ = 100 kΩ, R₂ = ∞, C₁ = 100 pF	4.5 to 5.5		0.11		%/°C
f_MAX	Maximum frequency		C₁ = 50 pF, R₁ = 3.5 kΩ, R₂ = ∞	3 to 3.6		24		MHz
			C₁ = 50 pF, R₁ = 3.5 kΩ, R₂ = ∞	4.5 to 5.5		24
			C₁ = 0 pF, R₁ = 9.1 kΩ, R2 = ∞	3 to 3.6		38
			C₁ = 0 pF, R₁ = 9.1 kΩ, R2 = ∞	4.5 to 5.5		38
	Center frequency (duty 50%)		C₁ = 40 pF, R₁ = 3 kΩ, R₂ = ∞, VCO_IN = V_CC/2	3 to 3.6	7	10		MHz
				4.5 to 5.5	12	17
				4.5⁽¹⁾	15⁽¹⁾		17.5⁽¹⁾
ΔfVCO	Frequency linearity		C₁ = 100 pF, R₁ = 100 kΩ, R₂ = ∞	3 to 3.6		0.4%
ΔfVCO	Frequency linearity		C₁ = 100 pF, R₁ = 100 kΩ, R₂ = ∞	4.5 to 5.5		0.4%
	Offset frequency		C₁ = 1 nF, R₂ = 220 kΩ	3 to 3.6		400		kHz
	Offset frequency		C₁ = 1 nF, R₂ = 220 kΩ	4.5 to 5.5		400		kHz
DEMODULATOR
V_OUT vs f_IN			C₁ = 100 pF, C₂ = 100 pF, R₁ = 100 kΩ, R₂ = ∞, R₃ = 100 kΩ	3		8		mV/kHz
V_OUT vs f_IN			C₁ = 100 pF, C₂ = 100 pF, R₁ = 100 kΩ, R₂ = ∞, R₃ = 100 kΩ	4.5		330		mV/kHz