Input signals can be up translated using the SN74LV4T125-Q1. The voltage applied at V_CC will determine the output voltage and the input thresholds as described in the Recommended Operating Conditions and Electrical Characteristics tables. When connected to a high-impedance input, the output voltage will be approximately V_CC in the HIGH state, and 0 V in the LOW state.

The inputs have reduced thresholds that allow for input HIGH state levels which are much lower than standard values. For example, standard CMOS inputs for a device operating at a 5-V supply will have a V_IH(MIN) of 3.5 V. For the SN74LV4T125-Q1, V_IH(MIN) with a 5-V supply is only 2 V, which would allow for up-translation from a typical 2.5-V to 5-V signals.

Ensure that the input signals in the HIGH state are above V_IH(MIN) and input signals in the LOW state are lower than V_IL(MAX) as shown in Figure 8-3.

Up Translation Combinations are as follows:

• 1.8-V V_CC – Inputs from 1.2 V
• 2.5-V V_CC – Inputs from 1.8 V
• 3.3-V V_CC – Inputs from 1.8 V and 2.5 V
• 5.0-V V_CC – Inputs from 2.5 V and 3.3 V

Figure 8-3 LVxT Up and Down Translation Example