ZHCSCA5C February   2014  – June 2022 SN74LV4T125

PRODUCTION DATA  

  1. 特性
  2. 应用范围
  3. 说明
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Noise Characteristics
    8. 6.8 Operating Characteristics
    9. 6.9 Typical Characteristics
  7. Parameter Measurement Information
    1. 7.1 18
  8. Detailed Description
    1. 8.1 Overview
      1. 8.1.1 Translating Down
      2. 8.1.2 Translating Up
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  9. Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Additional Product Selection
    2. 12.2 接收文档更新通知
    3. 12.3 支持资源
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 术语表
  13. 13Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

Additional Product Selection

DEVICEPACKAGEDESCRIPTION
SN74LV1T00DCK, DBV2‐Input Positive‐NAND Gate
SN74LV1T02DCK, DBV2‐Input Positive‐NOR Gate
SN74LV1T04DCK, DBVInverter Gate
SN74LV1T08DCK, DBV2‐Input Positive‐AND Gate
SN74LV1T34DCK, DBV, DRLSingle Buffer Gate
SN74LV1T14DCK, DBVSingle Schmitt‐Trigger Inverter Gate
SN74LV1T32DCK, DBV2‐Input Positive‐OR Gate
SN74LV1T86DCK, DBVSingle 2‐Input Exclusive‐Or Gate
SN74LV1T125DCK, DBV, DRLSingle Buffer Gate with 3‐state Output
SN74LV1T126DCK, DBV, DRLSingle Buffer Gate with 3‐state Output
SN74LV4T125RGY, PWQuadruple Bus Buffer Gate With 3‐State Outputs