3 Description

The SN74LV4T32-EP contains four independent 2-input OR Gates with Schmitt-trigger inputs. Each gate performs the Boolean function Y = A + B in positive logic. The output level is referenced to the supply voltage (V_CC) and supports 1.8-V, 2.5-V, 3.3-V, and 5-V CMOS levels.

The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example, 1.2 V input to 1.8 V output or 1.8 V input to 3.3 V output). In addition, the 5-V tolerant input pins enable down translation (for example, 3.3 V to 2.5 V output).

Package Information

PART NUMBER	PACKAGE⁽¹⁾	PACKAGE SIZE⁽²⁾	BODY SIZE (NOM)⁽³⁾
SN74LV4T32-EP	PW (TSSOP, 14)	5.00 mm × 6.40 mm	5.00 mm × 4.40 mm

(1) For all available packages, see the orderable addendum at the end of the data sheet.

(2) The package size (length × width) is a nominal value and includes pins, where applicable.

(3) The body size (length × width) is a nominal value and does not include pins.

Simplified Logic Diagram (Positive Logic)