ZHCSRA7K April   1998  – December 2022 SN74LV594A

PRODMIX  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Switching Characteristics: VCC = 2.5 V ± 0.2 V
    7. 6.7  Switching Characteristics: VCC = 3.3 V ± 0.3 V
    8. 6.8  Switching Characteristics: VCC = 5 V ± 0.5 V
    9. 6.9  Timing Requirements: VCC = 2.5 V ± 0.2 V
    10. 6.10 Timing Requirements: VCC = 3.3 V ± 0.3 V
    11. 6.11 Timing Requirements: VCC = 5 V ± 0.5 V
    12. 6.12 Noise Characteristics
    13. 6.13 Operating Characteristics
    14. 6.14 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 接收文档更新通知
    2. 10.2 支持资源
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 术语表
  11. 11Mechanical, Packaging, and Orderable Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • DB|16
  • PW|16
  • BQB|16
  • D|16
散热焊盘机械数据 (封装 | 引脚)
订购信息

6.11 Timing Requirements: VCC = 5 V ± 0.5 V

over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V. See Figure 6-1.
TA = 25°C SN74LV594A
–40°C TO 85°C		 SN74LV594A
–40°C TO 125°C		 UNIT
MIN MAX MIN MAX MIN MAX
tw Pulse duration RCLK or SRCLK high or low 5 5 6 ns
RCKR or SCRCLR low 5.2 5.2 6.2
tsu Setup time SER before SRCLK↑ 3 3 3.5 ns
SRCLK↑ before RCLK↑ 5 5 6
SCRCLR low before RCLK↑(1) 5 5 5.5
SRCLR high (inactive) before SRCLK↑ 2.9 3.3 4
RCLK high (inactive) before RCLK↑ 3.2 3.7 4.5
th Hold time SER after SRCLK↑ 2 2 2.5 ns
(1) This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case the shift register is one clock pulse ahead of the storage register.
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