8.3 Feature Description

Two 16-bit counters count up on each positive edge of the respective clock input. RCOA is set low when counter A is full count. Counter B clock is gated by the CCKBEN input. Connecting RCOA to CCKBEN together chains the counters to make one 32-bit counter.

Asynchronous CCLR input resets both counter to zero.

One 32-bit storage register records the contents of both counters on the rising edge of RCLK. The contents of the storage register are saved until the next rising edge of the RCLK.

Mapped output bus can be set to high impedance or output 8-bits of the 32-bit storage register.