米6体育平台手机版

SCLS589B August 2004 – May 2020 SN74LV8154

PRODUCTION DATA.

请参考 PDF 数据表获取器件具体的封装图。

5 Pin Configuration and Functions

N or PW Package

20-Pin PDIP or TSSOP

Top View

PIN		I/O	DESCRIPTION
NAME	NO.	I/O	DESCRIPTION
CCLR	11	I	Clock clear, asyncrounous active-low clear for both counters
CLKA	1	I	Clock A, rising edge count clock
CLKB	2	I	Clock B, rising edge count clock
CLKBEN	9	I	Clock B enable, active-low allows clocking for counter B; connect to RCOA for 32-bit counter.
GAL	3	I	Gate A lower byte, active-low puts lower byte of stored counter A on the Y bus.
GAU	4	I	Gate A upper byte, active-low puts upper byte of stored counter A on the Y bus.
GBL	5	I	Gate B lower byte, active-low puts lower byte of stored counter B on the Y bus.
GBU	6	I	Gate B upper byte, active-low puts upper byte of stored counter B on the Y bus.
GND	10	—	Ground
RCLK	7	I	Register Clock, rising edge stores counters into an internal storage register.
RCOA	8	O	Ready case overflow A, active low when counter A is full count and ready to overflow on next clock A.
V_CC	20	—	Power supply pin
Y0	19	O	Data output bit 0 (LSB)
Y1	18	O	Data output bit 1
Y2	17	O	Data output bit 2
Y3	16	O	Data output bit 3
Y4	15	O	Data output bit 4
Y5	14	O	Data output bit 5
Y6	13	O	Data output bit 6
Y7	12	O	Data output bit 7 (MSB)