9.1 Overview

This dual negative-edge-triggered J-K flip-flop is designed for 1.65-V to 3.6-V V_CC operation.

A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup-time requirements is transferred to the outputs on the negative-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the J and K inputs can be changed without affecting the levels at the outputs. The SN74LVC112A can perform as a toggle flip-flop by tying J and K high.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment.

9.2 Functional Block Diagram

Figure 4. Logic Diagram, Each Flip-Flop (Positive Logic)

9.3 Feature Description

• Wide operating voltage range
  • Operates from 1.65 V to 3.6 V
• Allows down voltage translation
  • Inputs accept voltages to 5.5 V
• I_off feature
  • Allows voltages on the inputs and outputs when V_CC is 0 V

9.4 Device Functional Modes