ZHCSG91U April 1999 – April 2017 SN74LVC1G79
PRODUCTION DATA.
- 1 特性
- 2 应用
- 3 说明
- 4 修订历史记录
- 5 Pin Configuration and Functions
-
6 Specifications
- 6.1 Absolute Maximum Ratings
- 6.2 ESD Ratings
- 6.3 Recommended Operating Conditions
- 6.4 Thermal Information
- 6.5 Electrical Characteristics
- 6.6 Timing Requirements: TA = -40°C to +85°C
- 6.7 Timing Requirements: TA = -40°C to +125°C
- 6.8 Switching Characteristics: CL = 15 pF, TA = -40°C to +85°C
- 6.9 Switching Characteristics: CL = 30 or 50 pF, TA = -40°C to +85°C
- 6.10 Switching Characteristics: CL = 30 pF or 50 pF, TA = -40°C to +125°C
- 6.11 Operating Characteristics
- 6.12 Typical Characteristics
- 7 Parameter Measurement Information
- 8 Detailed Description
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12器件和文档支持
- 13机械、封装和可订购信息
封装选项
请参考 PDF 数据表获取器件具体的封装图。
机械数据 (封装 | 引脚)
- DBV|5
- DCK|5
- DRL|5
- YZP|5
散热焊盘机械数据 (封装 | 引脚)
订购信息
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
9.1 Application Information
A useful application for the SN74LVC1G79 is using it as a data latch with low-voltage data retention. This application implements the use of a microcontroller GPIO pin to act as a clock to set the output state and a second GPIO to provide the input data. If the SN74LVC1G79 is being powered from 1.8 V and there is concern that a power glitch could exist as low as 1.5 V, the device will retain the state of the Q output. An example of this data retention is shown in Figure 8 where the VCC drops to 1.5 V and the Q output maintains the HIGH output state when VCC returns to 1.8 V. If the VCC voltage drops below 1.5 V, data retention is not guaranteed.
9.2 Typical Application
Figure 7. Low Voltage Data Retention With SN74LVC1G79
9.2.1 Design Requirements
The SN74LVC1G79 device uses CMOS technology and has balanced output drive. Take care to avoid bus contention because it can drive currents that would exceed maximum limits.
9.2.2 Detailed Design Procedure
- Recommended input conditions:
- For rise time and fall time specifications, see Δt/Δv in Recommended Operating Conditions.
- For specified high and low levels, see VIH and VIL in Recommended Operating Conditions.
- Input voltages are recommended to not go below 0 V and not exceed 5.5 V for any VCC. See Recommended Operating Conditions.
- Recommended output conditions:
- Load currents should not exceed ±50 mA. See Absolute Maximum Ratings.
- Output voltages are recommended to not go below 0 V and not exceed the VCC voltage. See Recommended Operating Conditions.
9.2.3 Application Curve
Figure 8. Data Retention With VCC Glitch Down to 1.5 V