ZHCSH07 April 2017 SN74LVC1G80-Q1
PRODUCTION DATA.
- 1 特性
- 2 应用
- 3 说明
- 4 修订历史记录
- 5 Pin Configuration and Functions
-
6 Specifications
- 6.1 Absolute Maximum Ratings
- 6.2 ESD Ratings
- 6.3 Recommended Operating Conditions
- 6.4 Thermal Information
- 6.5 Electrical Characteristics
- 6.6 Timing Requirements: TA = -40°C to +85°C
- 6.7 Timing Requirements: TA = -40°C to +125°C
- 6.8 Switching Characteristics: TA = -40°C to +85°C, CL = 15 pF
- 6.9 Switching Characteristics: TA = -40°C to +85°C, CL = 30 pF or 50 pF
- 6.10 Switching Characteristics: TA = -40°C to +125°C, CL = 30 pF or 50 pF
- 6.11 Operating Characteristics
- 6.12 Typical Characteristics
- 7 Parameter Measurement Information
- 8 Detailed Description
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12器件和文档支持
- 13机械、封装和可订购信息
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
9.1 Application Information
A useful application for the SN74LVC1G80-Q1 is using it as a frequency divider. By feeding back the output (Q) to the input (D), the output will toggle on every rising edge of the clock waveform. The output goes HIGH once every two clock cycles so essentially the frequency of the clock signal is divided by a factor of two. The SN74LVC1G80-Q1 does not have preset or clear functions so the initial state of the output is unknown. This application implements the use of a microcontroller GPIO pin to initially set the input HIGH, so the output LOW. Initialization is not needed, but should be kept in mind. Post initialization, the GPIO pin is set to a high impedance mode. Depending on the microcontroller, the GPIO pin could be set to an input and used to monitor the clock division.
9.2 Typical Application
Figure 7. Clock Frequency Division
9.2.1 Design Requirements
For this application, a resistor needs to be placed on the feedback line in order for the initialization voltage from the microcontroller to overpower the signal coming from the output (Q). Without it the state at the input would be challenged by the GPIO from the microcontroller and from the output of the SN74LVC1G80-Q1.
The SN74LVC1G80-Q1 device uses CMOS technology and has balanced output drive. Take care to avoid bus contention because it can drive currents that would exceed maximum limits.
9.2.2 Detailed Design Procedure
- Recommended input conditions:
- For rise time and fall time specifications, see Δt/Δv in Recommended Operating Conditions.
- For specified high and low levels, see VIH and VIL in Recommended Operating Conditions.
- Input voltages are recommended to not go below 0 V and not exceed 5.5 V for any VCC. See Recommended Operating Conditions.
- Recommended output conditions:
- Load currents should not exceed ±50 mA. See Absolute Maximum Ratings.
- Output voltages are recommended to not go below 0 V and not exceed the VCC voltage. See Recommended Operating Conditions.
- Feedback resistor:
- A 10-kΩ resistor is chosen here to bias the input so the microcontroller GPIO output can initialize the input and output. The resistor value is important because a resistance too high, say at 1 MΩ, would cause too much of a voltage drop, causing the output to no longer be able to drive the input. On the other hand, a resistor too low, such as a 1 Ω, would not bias enough and might cause current to flow into the microcontroller, possibly damaging the device.
9.2.3 Application Curve
Figure 8. Frequency Division