SCAS297N JANUARY 1993 – June 2014 SN74LVC540A
PRODUCTION DATA.
请参考 PDF 数据表获取器件具体的封装图。
These devices are ideal for driving bus lines or buffer memory address registers. These devices feature inputs and outputs on opposite sides of the package that facilitate printed circuit board layout. The 3-state control gate is a 2-input AND gate with active-low inputs so that, if either output-enable (OE1 or OE2) input is high, all outputs are in the high-impedance state. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment. These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
INPUTS | OUTPUT Y |
||
---|---|---|---|
OE1 | OE2 | A | |
L | L | L | H |
L | L | H | L |
H | X | X | Z |
X | H | X | Z |