The SN74LVCH32373A is a 32-bit transparent D-type latch that is designed for 1.65-V to 3.6-V V_CC operation.

A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.

OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

To ensure the high-impedance state during power up or power down, OE should be tied to V_CC through a pull-up resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pull-up or pull-down resistors with the bus-hold circuitry is not recommended.

Latches are arranged in banks of 8, with each bank having a separate latch enable (LE) and output enable ( OE) associated with it, as shown in the functional block diagram below.

When the latch enable pin for a bank is asserted (HIGH), the outputs will follow the data inputs.

When the latch enable pin for a bank is de-asserted (LOW), the outputs will continue to hold the valid input value at the time of switching.

When the output enable pin is asserted (LOW), the output is active.

When the output enable pin is de-asserted (HIGH), the output is disabled (high impedance). This does not affect the latch operation.