Add a decoupling capacitor from each supply pin (VCC) to a nearby GND pin. The capacitor needs to be placed physically close to the device and electrically close to both the VCC and GND pins. For BGA type packages, these capacitors are often placed on the back of the board to minimize trace length. Adding one capacitor per supply pin is recommended.
Ensure the capacitive load at the output is ≤ 70 pF. This is not a hard limit, however it will ensure optimal performance. This can be accomplished by providing short, appropriately sized traces from the SN74LVCH32373A to the receiving device.
Ensure the resistive load at the output is larger
than (VCC / 50 mA) Ω. This will ensure that the maximum output
current from the Absolute Maximum Ratings is not violated. Most CMOS inputs
have a resistive load measured in megaohms; much larger than the minimum
calculated above.
Thermal issues are rarely a concern for logic gates, however the power consumption and thermal increase can be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd Calculation. In multi-channel high-speed applications, it is possible to reach the thermal limits of the device without violating any other absolute maximum ratings.