SCBS778B November 2003 – June 2016 SN74LVTH16373-EP
PRODUCTION DATA.
- 1 Features
- 2 Applications
- 3 Description
- 4 Revision History
- 5 Pin Configuration and Functions
-
6 Specifications
- 6.1 Absolute Maximum Ratings
- 6.2 ESD Ratings
- 6.3 Recommended Operating Conditions
- 6.4 Thermal Information
- 6.5 Electrical Characteristics
- 6.6 Timing Requirements (I Version)
- 6.7 Switching Characteristics (I Version)
- 6.8 Timing Requirements (M Version)
- 6.9 Switching Characteristics (M Version)
- 6.10 Typical Characteristics
- 7 Parameter Measurement Information
- 8 Detailed Description
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
1 Features
- Controlled Baseline
- One Assembly/Test Site, One Fabrication Site
- Enhanced Diminishing Manufacturing Sources (DMS) Support
- Enhanced Product-Change Notification
- Qualification Pedigree (1)
- Member of the Texas Instruments Widebus™ Family
- State-of-the-Art Advanced BiCMOS Technology (ABT) Design for 3.3-V Operation and Low Static-Power Dissipation
- Supports Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC)
- Supports Unregulated Battery Operation Down to 2.7 V
- Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C
- Ioff and Power-Up Tri-State Support Hot Insertion
- Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
- Distributed VCC and GND Pins Minimize High-Speed Switching Noise
- Flow-Through Architecture Optimizes PCB Layout
- Latch-Up Performance Exceeds 500 mA Per JESD 17
- ESD Protection Exceeds JESD 22
- 4000-V Human Body Model (A114-A)
- 200-V Machine Model (A115-A)
2 Applications
- Data Buffer
- Bus Driver
- Display Driver
3 Description
The SN74LVTH16373 is a 16-bit transparent D-type latch with tri-state outputs designed for low-voltage (3.3 V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment.
This device is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. This device can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs.
Device Information(2)
| PART NUMBER | PACKAGE | BODY SIZE (NOM) |
|---|---|---|
| SN74LVTH16373-EP | TSSOP (48) | 12.50 mm × 6.10 mm |
| SSOP (48) | 15.88 mm × 7.49 mm | |
| BGA MICROSTAR JUNIOR (56) | 4.50 mm × 7.00 mm |
- Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.
- For all available packages, see the orderable addendum at the end of the data sheet.
SN74LVTH16373-EP Single Channel Block Diagram
