SCBS778B November   2003  – June 2016 SN74LVTH16373-EP

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements (I Version)
    7. 6.7  Switching Characteristics (I Version)
    8. 6.8  Timing Requirements (M Version)
    9. 6.9  Switching Characteristics (M Version)
    10. 6.10 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage –0.5 4.6 V
VI Input voltage(2) –0.5 7 V
VO Voltage applied to any output in the high-impedance or power-off state(2) –0.5 7 V
VO Voltage applied to any output in the high state(2) –0.5 VCC + 0.5 V V
IO Current into any output in the low state 128 mA
IO Current into any output in the high state(3) 64 mA
IIK Input clamp current (VI < 0) –50 mA
IOK Output clamp current (VO < 0) –50 mA
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(3) This current flows only when the output is in the high state and VO > VCC.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per A114-A ±4000 V
Charged device model (CDM), per JEDEC specification JESD22-C101(1) ±3000 V
Machine model (MM), per A115-A 200 V
(1) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage 2.7 3.6 V
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
VI Input voltage 5.5 V
IOH High-level output current –32 mA
IOL Low-level output current 64 mA
Δt/Δv Input transition rise or fall rate, outputs enabled 10 ns/V
Δt/ΔVCC Power-up ramp rate 200 µs/V
TA Operating ambient temperature I version –40 85 °C
M version –55 125 °C
(1) All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, SCBA004.

6.4 Thermal Information

THERMAL METRIC(1)(2) SN74LVTH16373-EP UNIT
DGG (TSSOP) DL (SSOP) GQL (BGA MICROSTAR JUNIOR)
48 PINS 48 PINS 56 PINS
RθJA Junction-to-ambient thermal resistance 68.9 60.3 62.5 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 14.6 31 24.7 °C/W
RθJB Junction-to-board thermal resistance 35.8 32.1 28.9 °C/W
ψJT Junction-to-top characterization parameter 2.4 9.3 0.9 °C/W
ψJB Junction-to-board characterization parameter 35.5 31.8 28 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.
(2) The package thermal impedance is calculated in accordance with JESD 51-7.

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted); all typical values are at VCC = 3.3 V, TA = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIK VCC = 2.7 V, II = –18 mA –1.2 V
VOH VCC = 2.7 V to 3.6 V, IOH = –100 µA VCC – 0.2 V
VCC = 2.7 V, IOH = –8 mA 2.4 V
VCC = 3 V, IOH = –32 mA 2 V
VOL VCC = 2.7 V IOL = 100 µA 0.2 V
IOL = 24 mA 0.5 V
VCC = 3 V, IOL = 16 mA 0.4 V
IOL = 32 mA 0.5 V
IOL = 64 mA 0.55 V
II VCC = 0 or 3.6 V, VI = 5.5 V 10 µA
Control inputs VCC = 3.6 V, VI = VCC or GND ±1 µA
Data inputs VCC = 3.6 V VI = VCC 1 µA
VI = 0 –5 µA
Ioff VCC = 0, VI or VO = 0 to 4.5 V ±100 µA
II(hold) Data inputs VCC = 3 V VI = 0.8 V 75 µA
VI = 2 V –75 µA
VCC = 3.6 V(1), VI = 0 to 3.6 V ±650 µA
IOZH VCC = 3.6 V, VO = 3 V 5 µA
IOZL VCC = 3.6 V, VO = 0.5 V –5 µA
IOZPU VCC = 0 to 1.5 V, VO = 0.5 to 3 V, OE = don’t care ±100 µA
IOZPD VCC = 1.5 V to 0, VO = 0.5 to 3 V, OE = don’t care ±100 µA
ICC VCC = 3.6 V, IO = 0, VI = VCC or GND Outputs high 0.19 mA
Outputs low 5 mA
Outputs disabled 0.19 mA
∆ICC(2) VCC = 3 to 3.6 V, One input at VCC − 0.6 V, Other inputs at VCC or GND 0.2 mA
Ci VI = 3 V or 0 3 pF
Co VO = 3 V or 0 9 pF
(1) This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
(2) This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.

6.6 Timing Requirements (I Version)

over recommended operating conditions (unless otherwise noted); TA = –40°C to 85°C
MIN MAX UNIT
tw Pulse duration, LE high VCC = 3.3 V ± 0.3 V 3 ns
VCC = 2.7 V 3 ns
tsu Setup time, data before LE↓ VCC = 3.3 V ± 0.3 V 1 ns
VCC = 2.7 V 0.6 ns
th Hold time, data after LE↓ VCC = 3.3 V ± 0.3 V 1 ns
VCC = 2.7 V 1.1 ns

6.7 Switching Characteristics (I Version)

over recommended operating conditions (unless otherwise noted); TA = –40°C to 85°C; all typical values are at VCC = 3.3 V, TA = 25°C
PARAMETER FROM (INPUT) TO (OUTPUT) TEST CONDITIONS MIN TYP MAX UNIT
tPLH D Q VCC = 3.3 V ± 0.3 V 1.5 2.7 3.8 ns
VCC = 2.7 V 4.2 ns
tPHL D Q VCC = 3.3 V ± 0.3 V 1.5 2.5 3.6 ns
VCC = 2.7 V 4 ns
tPLH LE Q VCC = 3.3 V ± 0.3 V 2.1 3 4.3 ns
VCC = 2.7 V 4.8 ns
tPHL LE Q VCC = 3.3 V ± 0.3 V 2.1 2.9 4 ns
VCC = 2.7 V 4 ns
tPZH OE Q VCC = 3.3 V ± 0.3 V 1.5 2.8 4.3 ns
VCC = 2.7 V 5.1 ns
tPZL OE Q VCC = 3.3 V ± 0.3 V 1.5 2.8 4.3 ns
VCC = 2.7 V 4.7 ns
tPHZ OE Q VCC = 3.3 V ± 0.3 V 2.4 3.5 5 ns
VCC = 2.7 V 5.4 ns
tPLZ OE Q VCC = 3.3 V ± 0.3 V 2 3.2 4.7 ns
VCC = 2.7 V 4.8 ns
tsk(o) VCC = 3.3 V ± 0.3 V 0.5 ns

6.8 Timing Requirements (M Version)

over recommended operating conditions (unless otherwise noted); TA = –55°C to 125°C
MIN MAX UNIT
tw Pulse duration, LE high VCC = 3.3 V ± 0.3 V 3 ns
VCC = 2.7 V 3 ns
tsu Setup time, data before LE↓ VCC = 3.3 V ± 0.3 V 1.6 ns
VCC = 2.7 V 1 ns
th Hold time, data after LE↓ VCC = 3.3 V ± 0.3 V 1.4 ns
VCC = 2.7 V 1.5 ns

6.9 Switching Characteristics (M Version)

over recommended operating conditions (unless otherwise noted); TA = –55°C to 125°C; all typical values are at VCC = 3.3 V, TA = 25°C
PARAMETER FROM (INPUT) TO (OUTPUT) TEST CONDITIONS MIN TYP MAX UNIT
tPLH D Q VCC = 3.3 V ± 0.3 V 1.5 2.7 5 ns
VCC = 2.7 V 5.5 ns
tPHL D Q VCC = 3.3 V ± 0.3 V 1.5 2.5 4.8 ns
VCC = 2.7 V 5.3 ns
tPLH LE Q VCC = 3.3 V ± 0.3 V 2.1 3 5.4 ns
VCC = 2.7 V 5.9 ns
tPHL LE Q VCC = 3.3 V ± 0.3 V 2.1 2.9 4.9 ns
VCC = 2.7 V 4.9 ns
tPZH OE Q VCC = 3.3 V ± 0.3 V 1.5 2.8 7 ns
VCC = 2.7 V 7.9 ns
tPZL OE Q VCC = 3.3 V ± 0.3 V 1.5 2.8 6.2 ns
VCC = 2.7 V 7.2 ns
tPHZ OE Q VCC = 3.3 V ± 0.3 V 1.8 3.5 7.2 ns
VCC = 2.7 V 7.9 ns
tPLZ OE Q VCC = 3.3 V ± 0.3 V 2 3.2 5.2 ns
VCC = 2.7 V 5.4 ns
tsk(o) VCC = 3.3 V ± 0.3 V 0.5 ns
SN74LVTH16373-EP D004_derating_SCBS778.gif
1. See data sheet for absolute maximum and minimum recommended operating conditions.
2. Silicon operating life design goal is 10 years at 105°C junction temperature (does not include package interconnect life).
3. Enhanced plastic product disclaimer applies.
Figure 1. Derating Chart for SN74LVTH16373-EP

6.10 Typical Characteristics

SN74LVTH16373-EP D001_VOH_SCBS778.gif
Figure 2. VOH vs Temperature
SN74LVTH16373-EP D002_VOL_SCBS778.gif
Figure 3. VOL vs Temperature
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