Each data input on this device includes a weak latch that maintains a valid logic level on the input. The state of these latches is unknown at startup and remains unknown until the input has been forced to a valid high or low state. After data is sent through a channel, the latch maintains the previous state on the input (if the line is left floating). It is not recommended to use pull-up or pull-down resistors together with a bus-hold input, as it may cause undefined inputs to occur which leads to excessive current consumption.

Bus-hold data inputs prevent floating inputs on this device. The Implications of Slow or Floating CMOS Inputs application report explains the problems associated with leaving the CMOS inputs floating. These latches remain active at all times, independent of all control signals such as direction control or output enable. The latches also remain active when the device is in the partial power down state, corresponding supply is still present, or when the I/O's are floated. The Bus-Hold Circuit application report has additional details regarding bus-hold inputs.

Figure 8-3 Schematic Description of Location of Bus-Hold Circuits