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SLRS023E December 1976 – January 2015 SN75468 , SN75469

PRODUCTION DATA.

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机械数据 (封装 | 引脚)

N|16
D|16

散热焊盘机械数据 (封装 | 引脚)

订购信息

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

		MIN	MAX	UNIT
V_CE	Collector-emitter voltage		100	V
V_I	Input voltage⁽²⁾		30	V
	Peak collector current		500	mA
I_OK	Output clamp current		500	mA
	Total emitter-terminal current		–2.5	A
T_J	Operating virtual junction temperature		150	°C
T_stg	Storage temperature range	–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to the emitter/substrate terminal E, unless otherwise noted.

7.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged device model (CDM), per JEDEC specification JESD22-C101, all pins⁽²⁾	±500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	MAX	UNIT
V_I		0	5	V
V_CC		0	100	V
T_J	Junction Temperature	–40	125	°C

7.4 Thermal Information

THERMAL METRIC⁽¹⁾		SN7546x	UNIT
		D
		16 PINS
R_θJA	Junction-to-ambient thermal resistance	73	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	40.3
R_θJB	Junction-to-board thermal resistance	38.9
ψ_JT	Junction-to-top characterization parameter	10.9
ψ_JB	Junction-to-board characterization parameter	38.7
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	N/A

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

T_A = 25°C (unless otherwise noted)

PARAMETER		TEST CONDITIONS⁽¹⁾		SN75468			SN75469			UNIT
PARAMETER		TEST CONDITIONS⁽¹⁾		MIN	TYP	MAX	MIN	TYP	MAX	UNIT
V_I(on)	On-state input voltage	V_CE = 2 V	I_C = 125 mA							V
			I_C = 200 mA			2.4
			I_C = 250 mA			2.7
			I_C = 275 mA
			I_C = 300 mA			3
			I_C = 350 mA
V_CE(sat)	Collector-emitter saturation voltage	I_I = 250 µA, IC = 100 mA			0.9	1.1		0.9	1.1	V
		I_I = 350 µA, IC = 100 mA			1	1.3		1	1.3
		I_I = 500 µA, IC = 100 mA			1.2	1.6		1.2	1.6
V_F	Clamp-diode forward voltage	I_F = 350 mA			1.7	2		1.7	2	V
I_CEX	collector cutoff current	V_CE = 100 V, I_I = 0				50			50	µA
		V_CE = 100 V, TA = 70°C	I_I = 0			100			100
		V_CE = 100 V, TA = 70°C	V_I = 1 V						500
I_I(off)	Off-state input current	V_CE = 50 V, I_C = 500 µA, T_A = 70°C		50	65		50	65		µA
I_I	Input current	V_I = 3.85 V			0.93	1.35				mA
		V_I = 5 V						0.35	0.5
		V_I = 12 V						1	1.45
I_R	Clamp-diode reverse current	V_R = 100 V				50			50	µA
I_R	Clamp-diode reverse current	V_R = 100 V, T_A = 70°C				100			10	µA
C_i	Input Capacitance	V_I = 0, f = 1 MHz			15	25		15	25	pF

(1) All electrical characteristics are measured with 0.1-µF capacitors connected at REF, CT, and V_CC to GND.

7.6 Switching Characteristics

T_A = 25°C free-air temperature

PARAMETER		TEST CONDITIONS⁽¹⁾	MIN	TYP	MAX	UNIT
t_PLH	Propagation delay time, low-to-high-level output	V_S = 20 V, R_L = 163 Ω, C_L = 15 pF, See Figure 14		0.25	1	µs
t_PHL	Propagation delay time, high-to-low-level output	V_S = 20 V, R_L = 163 Ω, C_L = 15 pF, See Figure 14		0.25	1	µs
V_OH	High-level output voltage after switching	V_S = 50 V, I_O = 300 mA, See Figure 14	V_S – 20			mV

(1) All switching characteristics are measured with 0.1-µF capacitors connected at REF and V_CC to GND.

7.7 Typical Characteristics

Figure 1. Collector-Emitter Saturation Voltage
vs
Collector Current (One Darlington)

Figure 3. Output Current vs Input Current

Figure 5. N Package Maximum Collector Current
vs
Duty Cycle

Figure 2. Collector-Emitter Saturation Voltage
vs
Total Collector Current (Two Darlingtons in Parallel)

Figure 4. D Package Maximum Collector Current
vs
Duty Cycle