SLLS977F April   2009  – July 2017 SN75DP139

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics (Device Power)
    6. 6.6  Electrical Characteristics (Hot Plug Detect)
    7. 6.7  Electrical Characteristics (Aux / I2C Pins)
    8. 6.8  Electrical Characteristics (TMDS and Main Link Pins)
    9. 6.9  Switching Characteristics (Hot Plug Detect)
    10. 6.10 Switching Characteristics (Aux / I2C Pins)
    11. 6.11 Switching Characteristics (TMDS and Main Link Pins)
    12. 6.12 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Hot Plug Detect
      2. 7.3.2 Aux / I2C Pins
      3. 7.3.3 TMDS and Main Link Pins
      4. 7.3.4 Input/Output Equivalent Circuits
    4. 7.4 Device Functional Modes
      1. 7.4.1 Active
      2. 7.4.2 Low Power With DDC Channel Enabled
      3. 7.4.3 Low Power
    5. 7.5 Programming
      1. 7.5.1 I2C Interface Notes
      2. 7.5.2 General I2C Protocol
      3. 7.5.3 Slave Address
        1. 7.5.3.1 Sink Port Selection Register And Source Plug-In Status Register Description (Sub-Address)
        2. 7.5.3.2 Example - Reading From The SN75DP139:
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 DVI Application
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Layer Stack
      2. 10.1.2 Differential Traces
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

5 Pin Configuration and Functions

48-Pin VQFN
RGZ Package
(Top View)
SN75DP139 rgz_pack_llsE54.gif
40-Pin WQFN
RSB Package
(Top View)
SN75DP139 rsb_po1_lls977.gif

Pin Functions

PIN I/O DESCRIPTION
SIGNAL NO.
RGZ RSB
MAIN LINK INPUT PINS
IN_D1 38, 39 1, 2 I DisplayPort Main Link Channel 0 Differential Input
IN_D2 41, 42 4, 5 I DisplayPort Main Link Channel 1 Differential Input
IN_D3 44, 45 6, 7 I DisplayPort Main Link Channel 2 Differential Input
IN_D4 47, 48 9, 10 I DisplayPort Main Link Channel 3 Differential Input
MAIN LINK PORT B OUTPUT PINS
OUT_D1 23, 22 30, 29 O TMDS Data 2 Differential Output
OUT_D2 20, 19 27, 26 O TMDS Data 1 Differential Output
OUT_D3 17, 16 25, 24 O TMDS Data 0 Differential Output
OUT_D4 14, 13 22, 21 O TMDS Data Clock Differential Output
HOT PLUG DETECT PINS
HPD_SOURCE 7 16 O Hot Plug Detect Output
HPD_SINK 30 35 I Hot Plug Detect Input
AUXILIARY DATA PINS
SDA_SOURCE, SCL_SOURCE 8, 9 17, 18 I/O Source Side Bidirectional DisplayPort Auxiliary Data Line
SDA_SINK, SCL_SINK 29, 28 34, 33 I/O TMDS Port Bidirectional DDC Data Lines
CONTROL PINS
OE_N 25 31 I Output Enable and power saving function for High Speed Differential level shifter path.
NC 10 11, 20, 40 No Connect
OVS 35 39 I DDC I2C buffer offset select
DDC_EN 32 36 I Enables or Disables the DDC I2C buffer
HPDINV 34 38 I HPD_SOURCE Logic and Level Select
VSadj 6 15 I TMDS Compliant Voltage Swing Control
SRC 3 13 I TMDS outputs rise and fall time select
I2C_EN 4 14 I Internal I2C register enable, used for HDMI / DVI connector differentiation
SUPPLY AND GROUND PINS
VCC 2, 11, 15, 21, 26,
33, 40, 46 		3, 8, 12, 19, 23
28, 32, 37		 3.3 V Supply
GND 1, 5, 12, 18, 24,
27, 31, 36, 37, 43(1)		 Thermal Pad Ground
(1) Connect the Thermal Pad to GND

Table 1. Control Pin Lookup Table

SIGNAL LEVEL(1) STATE DESCRIPTION
OE_N H Power Saving Mode Main Link is disabled. IN_Dx termination = 50 Ω with common mode voltage set to 0V.
OUT_Dx outputs = high impedance
L Normal Mode IN_Dx termination = 50 Ω
OUT_Dx outputs = active
I2C_EN H HDMI The Internal I2C register is active and readable when the TMDS port is selected indicating that the connector being used is HDMI.
This mode selects the fastest rise and fall time for the TMDS differential output signals
L DVI The Internal I2C register is disabled and not readable when the TMDS port is selected indicating that the connector being used is DVI.
This mode selects a slower rise and fall time for the TMDS differential output signals
See Application Information.
VSadj 4.02 kΩ ±5% Output Voltage Swing Contol Driver output voltage swing precision control to aid with system compliance
HPDINV H HPD Inversion HPD_SOURCE VOH =0.9V (typical) and HPD logic is inverted
L HPD non-inversion HPD_SOURCE VOH =3.2V (typical) and HPD logic is non-inverted
SRC H Edge Rate: Slowest SRC helps to slow down the rise and fall time. SRC =High adds ~60ps to the rise and fall time of the TMDS differential output signals in addition to the I2C_EN pin selection (recommended setting)
L Edge Rate: Slow SRC helps to slow down the rise and fall time. SRC =Low adds ~30ps to the rise and fall time of the TMDS differential output signals in addition to the I2C_EN pin selection
Hi-Z Edge Rate Leaving the SRC pin High Z, will keep the default rise and fall time of the TMDS differential output signals as selected by the I2C_EN pin.
It is recommended that an external resistor-divider (less than 100 kΩ) is used so that voltage on this pin = VCC/2, if Hi-Z logic level is intended on this pin.
OVS H Offset 1 DDC source side VOL and VIL offset range 1
L Offset 2 DDC source side VOL and VIL offset range 2
Hi-Z Offset 3 DDC source side VOL and VIL offset range 3
It is recommended that an external resistor-divider (less than 100 kΩ) is used so that voltage on this pin = VCC/2, if Hi-Z logic level is intended on this pin.
DDC_EN H DDC Buffer enabled DDC Buffer is enabled
L DDC buffer disabled DDC Buffer is disabled
(1) (H) Logic High; (L) Logic Low; (Z) High Z
千亿体育app官网登录(中国)官方网站IOS/安卓通用版/手机APP | 米乐app下载官网（中国）|ios|Android/通用版APP最新版 | 米乐|米乐·M6（中国大陆）官方网站 | 千亿体育登陆地址 | 华体会体育（中国）HTH·官方网站 | 千赢qy国际_全站最新版千赢qy国际V6.2.14安卓/IOS下载 | 18新利网v1.2.5|中国官方网站 | bob电竞真人（中国官网）安卓/ios苹果/电脑版【1.97.95版下载】 | 千亿体育app官方下载(中国)官方网站IOS/安卓/手机APP下载安装 |