ZHCSE15F July 2015 – May 2018 SN65DP159 , SN75DP159
PRODUCTION DATA.
The SNx5DP159 solves sink- or source-level issues by implementing a master/slave control mode for the DDC bus. When the SNx5DP159detects the start condition on the DDC bus from the SDA_SRC/SCL_SRC, it will transfer the data or clock signal to the SDA_SNK/SCL_SNK with little propagation delay. When SDA_SNK detects the feedback from the downstream device, the SNx5DP159 will pull up or pull down the SDA_SRC bus and deliver the signal to the source.
The DDC link defaults to 100 kbps, but can be set to various values including 400 kbps by setting the correct value to address 22h (see Table 3) through the I2C access on the DDC interface. The DDC lines are 5-V tolerant. The HPD_SRC goes to high impedance when VCC is under low power conditions, < 1.5-V.
NOTE
The SNx5DP159 uses clock stretching for DDC transactions. As there are sources and sinks that do no perform this function correctly a system may not work correctly as DDC transactions are incorrectly transmitted/received. To overcome this a snoop configuration can be implemented where the SDA/SCL from the source is connected directly to the SDA/SCL sink. The SNx5DP159 will need its SDA_SNK and SCL_SNK pins connected to this link in order to the SNx5DP159 to configure the TMDS_CLOCK_RATIO_STATUS bit. Care must be taken when this configuration is being implemented as the voltage levels for DDC between the source and sink may be different, 3.3 V vs 5 V.