SNLS666 January 2020 SN75LVPE4410
PRODUCTION DATA.
The SN75LVPE4410 deploys an RX detect state machine that governs the RX detection cycle as defined in the PCI express specifications. At power up, after a manually triggered event through PWDN1 and PWDN2 pins (in pin mode), or writing to the relevant I2C / SMBus register, the redriver determines whether or not a valid PCI express termination is present at the far end of the link. The RX_DET pin of SN75LVPE4410 provides additional flexibility for system designers to appropriately set the device in desired mode according to Table 3.
If all four channels of SN75LVPE4410 are used for same PCI express link, the PRWDN1 and PWDN2 pin can be shorted and driven together.
| PWDN1 and PWDN2 | RXDET | COMMENTS |
|---|---|---|
| L | L0 | PCI Express RX detection state machine is enabled. RX detection is asserted after 2x valid detections.
Pre Detect: Hi-Z, Post Detect: 50 Ω. |
| L | L1 | PCI Express RX detection state machine is enabled. RX detection is asserted after 3x valid detections.
Pre Detect: Hi-Z, Post Detect: 50 Ω. |
| L | L2 (Float) | PCI Express RX detection state machine is enabled. RX detection is asserted after 1x valid detection.
Pre Detect: Hi-Z, Post Detect: 50 Ω. |
| L | L3 | PCI Express RX detection state machine is disabled.
Recommended for non PCI Express interface use case where the SN75LVPE4410 is used as buffer with equalization. Always 50 Ω. |
| H | X | Manual reset, input is high impedance. |