SNLS666 January   2020 SN75LVPE4410

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Typical Application
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics
    6. 6.6 High Speed Electrical Characteristics
    7. 6.7 SMBUS/I2C Timing Charateristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Linear Equalization
      2. 7.3.2 DC Gain
      3. 7.3.3 Receiver Detect State Machine
    4. 7.4 Device Functional Modes
      1. 7.4.1 Active PCIe Mode
      2. 7.4.2 Active Buffer Mode
      3. 7.4.3 Standby Mode
    5. 7.5 Programming
      1. 7.5.1 Control and Configuration Interface
        1. 7.5.1.1 Pin Mode
          1. 7.5.1.1.1 Four-Level Control Inputs
        2. 7.5.1.2 SMBUS/I2C Register Control Interface
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 PCIe x4 Lane Configuration
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VDD Supply voltage, VDD to GND DC plus AC power should not exceed these limits 3.0 3.3 3.6 V
NVDD Supply noise tolerance Supply noise, DC to <50 Hz, sinusoidal1 250 mVpp
Supply noise, 50 Hz to 10 MHz, sinusoidal1 20 mVpp
Supply noise, >10 MHz, sinusoidal1 10 mVpp
TRampVDD VDD supply ramp time From 0 V to 3.0 V 0.150 100 ms
TA Operating ambient temperature 0 70 C
PWLVCMOS Minimum pulse width required for the device to detect a valid signal on LVCMOS inputs PWDN1/2 200 μs
VDDSMBUS SMBus SDA and SCL Open Drain Termination Voltage Supply voltage for open drain pull-up resistor 3.6 V
FSMBus SMBus clock (SCL) frequency in SMBus slave mode 10 400 kHz
VIDLAUNCH Source differential launch amplitude 800 1200 mVpp
DR Data rate SN75LVPE4410 1 16 Gbps
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